Method for generating gate-level netlist and standard delay file and checking and correcting false routes

Abstract

The invention provides a method for generating a gate-level netlist and a standard delay file and checking and correcting false routes. The method for generating the gate-level netlist and standard delay file comprises the steps: acquiring all false routes; for each false route, executing the following operations: obtaining all fan-in and fan-out of each object on the false route, analyzing whether delay points exist in the fan-in and fan-out of each object, if so, defining no delay point to the false route any more, and if not, defining delay points according to the type of a time sequence arc between the fan-in and fan-out; and defining delay values to the delay points of the false route and writing a standard delay file and a modified gate-level netlist. Delay is added to the delay points so as to generate the standard delay file and the modified gate-level netlist and further check the set correctness of the false routes, so that the serious problems in the false routes can be found out before layout wiring is carried out, the layout wiring production period can be shortened, and the repeated layout wiring can be avoided.

Description

technical field [0001] The present invention relates to system-on-chip (SOC) back-end design, more particularly, relate to the gate-level netlist that generates standard delay file and modification and the gate that uses this standard delay file and modification in the pre-simulation stage in SOC back-end design process Level netlist checking and methods for correcting false paths. Background technique [0002] figure 1 is to illustrate the main steps of a traditional system-on-chip (SOC) back-end design flow. [0003] In step S1010, a digital logic circuit written in a hardware description language (HDL) is synthesized to generate a gate-level netlist. In this step, the mapping between the synthesizable register transfer level description and the synthesis library unit can be completed according to timing constraints and other conditions, so as to convert the hardware description language description of the digital logic circuit into a gate-level netlist. [0004] In ste...

AI Technical Summary

Problems solved by technology

This analysis process usually includes multiple post-simulation verifications and multiple engineering changes, which will greatly increase the production cycle of layout and routing

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