Semiconductor package structure and manufacturing method thereof

Abstract

A method of manufacturing a semiconductor package structure is provided, comprising the steps that a chip is provided; an active surface of the chip is disposed on a carrier; a molding compound is formed on the carrier with a metal layer disposed thereon, the metal layer has an upper and lower surface, multiple cavities formed on the upper surface and multiple protrusions formed on the lower surface and corresponding to the cavities, the protrusions are embedded in the molding compound, the metal layer is patterned to form multiple pads on a portion of the molding compound, the carrier and the molding compound are separated, multiple through holes are formed on the molding compound exposing the protrusions; a redistribution layer is formed on the molding compound and the active surface of the chip; multiple solder balls are formed on the redistribution layer, and a portion of the solder balls are correspondingly disposed to the pads.

Description

technical field [0001] The present invention relates to a semiconductor element and its manufacturing method, and in particular to a semiconductor packaging structure and its manufacturing method. Background technique [0002] The purpose of chip packaging is to protect the bare chip, reduce the density of chip contacts and provide good heat dissipation for the chip. When the number of contacts of the chip continues to increase, while the area of ​​the chip is getting smaller and smaller, it is bound to be difficult to redistribute all the contacts of the chip on the surface of the chip in a matrix, even if the surface of the chip can accommodate all the contacts. , will also cause the distance between the contacts to be too small, which will affect the electrical reliability of the subsequent welding of the solder balls. [0003] Therefore, the known technology proposes that the chip can be packaged with encapsulant to increase the area of ​​the chip, wherein the active su...

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Problems solved by technology

Due to the phenomenon of glue overflow during packaging, the encapsulation glue extends to part of the active surface of the chip and contaminates the active surface of the chip, so this method cannot be applied to CMOS chips

[0004] Furthermore, the above-mentioned method cannot package multiple semiconductor elements (such as chips) in the same package structure by vertical stacking.

Since it is known to increase the area design of the chip by encapsulating the chip with encapsulation gel, but the reconfiguration circuit layer is only located on the active surface of the chip and the bottom surface of the encapsulation compound, so it is impossible to stack the chips in the form of stacking

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