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A CMOS circuit structure, its preparation method and display device

A circuit structure and semiconductor technology, applied in circuits, electrical components, electrical solid devices, etc., can solve the problems of high production cost, complex production process, increase production cost, etc., to reduce production cost, simplify production process, and extend service life. Effect

Active Publication Date: 2015-08-05
BOE TECH GRP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0016] In the above-mentioned process of preparing CMOS circuits using the LTPS process, it is necessary to use at least 10 or more photoresist masks and at least 4 or more doping processes (P-type ion doping, N-type ion doping, LDD doping, etc.) and Ch doping), the production process is complex, the production cost is high, and, in step 1, the entire layer of a-Si material needs to be laser crystallized to obtain polysilicon material, and the long-time laser crystallization process will increase the product’s Production cost, and will reduce the service life of the laser tube, but also increase the production cost

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  • A CMOS circuit structure, its preparation method and display device
  • A CMOS circuit structure, its preparation method and display device
  • A CMOS circuit structure, its preparation method and display device

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Embodiment Construction

[0035] The specific implementation manners of the CMOS circuit structure provided by the embodiments of the present invention, its manufacturing method and the display device will be described in detail below with reference to the accompanying drawings.

[0036] The shape and size of each region in the drawings do not reflect the real scale of the CMOS circuit structure, but are only intended to schematically illustrate the content of the present invention.

[0037] A kind of CMOS circuit structure that the embodiment of the present invention provides, such as figure 2 As shown, there is a PMOS region C and an NMOS region D, including: a PMOS semiconductor layer 22, a gate insulating layer 23, a PMOS gate 24 and an NMOS gate 25, and a first interlayer dielectric layer 26 located on the base substrate 21 in sequence. , NMOS semiconductor layer 27, second interlayer dielectric layer 28, PMOS source and drain electrodes 29 and NMOS source and drain electrodes 30, wherein,

[00...

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Abstract

Provided are a CMOS circuit structure, a preparation method thereof and a display device, wherein a PMOS region in the CMOS circuit structure is of a LTPS TFT structure, that is, the PMOS semiconductor layer is prepared from a P type doped polysilicon material; an NMOS region is of an Oxide TFT structure, that is, the NMOS semiconductor layer is made of an oxide material; three doping processes applied to the NMOS region during the LTPS process may be omitted in the case in which the NMOS semiconductor layer in the NMOS region is made of an oxide material instead of the polysilicon material, which may simplify the preparation of the CMOS circuit structure as well as reduce a production cost. Furthermore, it is only required to crystallizing the PMOS semiconductor layer, which may also extend the lifespan of laser tube, contributing to reduction of the production cost.

Description

technical field [0001] The invention relates to the technical field of circuit manufacturing, in particular to a CMOS circuit structure, a preparation method thereof and a display device. Background technique [0002] Complementary Metal Oxide Semiconductor (CMOS, Complementary Metal Oxide Semiconductor) is composed of P-channel Metal Oxide Semiconductor (PMOS, Positive channel MetalOxide Semiconductor) and N-channel Metal Oxide Semiconductor (NMOS, Negativechannel-Metal-Oxide-Semiconductor). constitute. [0003] At present, low temperature polysilicon (LTPS, Low Temperature Poly-silicon) technology is generally used to prepare the semiconductor layers of the PMOS region and the NMOS region in the CMOS circuit respectively. The preparation process is relatively complicated, and the specific process steps are as follows: [0004] Step 1: On the base substrate 01, use a patterning process to form the pattern of the PMOS semiconductor layer 02 located in the PMOS area A, and t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/092H01L21/77H01L21/8258
CPCH01L27/1225H01L29/7869H01L27/1251
Inventor 任章淳
Owner BOE TECH GRP CO LTD