Standard cell library layout design method, layout method and standard cell library

Abstract

The invention provides a domain design method of a standard unit library. The method includes determining domain design basic parameter of the standard unit library. A substrate connection unit is used for providing substrate voltage for standard units in the standard unit library, and the domain design basic parameter of the standard units in the standard unit library does not comprise a substrate connection bus. The method further includes determining the domain of a substrate connection unit according to the domain design basic parameter and the domain design rule of the substrate connection unit. The standard unit library is further provided. The standard unit library comprises the substrate connection unit. A domain layout method of the standard unit library is further provided. The methods and the standard unit library can optimize transistor size in the standard units and increase wire distribution resources in the domain of the standard units.

Description

technical field [0001] The invention relates to the technical field of standard cell library design, in particular to a standard cell library layout design method, a layout method and a standard cell library. Background technique [0002] The standard cell library is the basis for the automated design of VLSI (Very LargeScale Integration). The application of the optimized standard cell library can automatically perform logic synthesis and layout layout and routing to improve design efficiency. [0003] The design method of the standard cell library in the prior art, comprises the following steps: [0004] Step 101, the scheme design of the standard cell library, determining various technical indicators of the cell library such as the basic design size of circuit devices, the highest frequency of the entire set of standard cell library, etc. according to the purpose of the standard cell library and the oriented process; [0005] Step 102, the circuit design of the standard c...

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Problems solved by technology

[0008] like figure 1 Shown is a schematic diagram of the layout structure of a standard cell in the prior art, from figure 1 It can be seen that the substrate voltage is provided for the standard cell through the substrate connection bus in the layout structure of the standard cell. The substrate connection bus occupies part of the wiring resources, so the size of the transistor is obviously limited, resulting in the standard cell. Reduced routing resources

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