Low-differential-pressure voltage stabilizer circuit with auxiliary circuit

[0030] It can be known from the background technology that a low dropout voltage regulator is usually used in electronic equipment to provide a stable working voltage for the working circuit, but the state of the working circuit changes, especially when the working circuit of the digital circuit changes from an on state to an off state. However, a sudden decrease in the load current will cause a large overshoot in the output voltage signal of the low dropout regulator. Although the prior art can reduce the voltage overshoot by setting a decoupling capacitor at the output end of the low dropout regulator, However, due to cost considerations, the decoupling capacitors described are usually small and not effective.

[0031] To this end, the present invention provides a low-dropout voltage regulator circuit with auxiliary circuits, please refer to figure 2 , The low-dropout regulator circuit with auxiliary circuit includes: a low-dropout regulator 201, and the output terminal of the low-dropout regulator 201 outputs a voltage signal V out Source follower PMOS transistor 202, the source of the source follower PMOS transistor 202 is connected to the output terminal of the low dropout regulator for the voltage signal V out When overshooting, reduce the voltage overshoot; the bias circuit 203, the output terminal of the bias circuit 203 is connected to the gate of the source follower PMOS transistor 202, used for the source follower PMOS transistor 202 Provide bias voltage V bias , The bias voltage V bias It is close to the threshold voltage of the source follower PMOS transistor.

[0032] In this technical solution, the source of the source follower PMOS transistor 202 is connected to the output terminal of the low dropout voltage regulator 201. When the load current of the low dropout voltage regulator 201 suddenly decreases, the low dropout voltage The voltage signal at the output terminal of the regulator 201 has an overshoot. At this time, the source voltage of the source follower PMOS transistor 202 rises, and the working current of the source follower PMOS transistor 202 rises rapidly in a short time, generating a pull-down current. The voltage overshoot of the voltage signal is reduced.

[0033] The specific embodiments are described in detail below in conjunction with the accompanying drawings, and the above-mentioned objectives and advantages of the present invention will be more clear.

[0034] Please refer to image 3 , image 3 It is a schematic structural diagram of a low-dropout regulator circuit with auxiliary circuits according to an embodiment of the present invention. The low dropout voltage regulator circuit with auxiliary circuit includes: a low dropout voltage regulator 301, a source follower PMOS transistor 302, and a bias circuit 303.

[0035] The output terminal of the low dropout regulator 301 outputs a voltage signal V out. The low dropout voltage regulator 301 usually includes a reference voltage unit, a voltage divider resistor, and an error amplifier (not shown in the figure). Its basic principle is to compare the reference voltage and the voltage divider resistor to divide the output voltage through the error amplifier. Stabilize the level of the output voltage signal. The specific implementation circuit of the low dropout voltage regulator 301 can refer to the prior art, which will not be repeated here. The voltage signal V output from the output terminal of the low dropout regulator 301 out When the load current is suddenly reduced, a large overshoot voltage will appear, causing the gate oxide layer of the MOS transistor with a low breakdown voltage to break down. Therefore, it is necessary to control the overshoot amount of the overshoot voltage.

[0036] The output terminal of the bias circuit 303 is connected to the gate of the source follower PMOS transistor 302, and is used to provide a bias voltage V for the source follower PMOS transistor 302 bias , The bias voltage V bias It is close to the threshold voltage of the source follower PMOS transistor 302.

[0037] In this embodiment, the bias circuit 303 includes a buffer amplifier BF, a first PMOS transistor PM1, and a first current source CS1. The input terminal of the first current source CS1 is connected to a power source, and the output of the first current source CS1 Is connected to the inverting input terminal of the buffer amplifier BF and the source of the first PMOS transistor PM1; the gate of the first PMOS transistor PM1 is connected to the output terminal of the buffer amplifier BF, and the first PMOS transistor The drain of PM1 is grounded; the positive input terminal of the buffer amplifier BF is connected to the output terminal of the low dropout regulator 301, and the output terminal of the buffer amplifier BF outputs the bias voltage V bias. The bias voltage V bias It is close to the threshold voltage of the source follower PMOS transistor 302. In this embodiment, the bias voltage V bias It is greater than the threshold voltage of the source follower PMOS transistor by 20 millivolts.

[0038] Since the non-inverting input terminal of the buffer amplifier BF is connected to the output terminal of the low dropout regulator 301, that is, the source of the source follower PMOS transistor 302, the inverting input terminal of the buffer amplifier BF is connected to the The source of the first PMOS transistor PM1, and the output terminal of the buffer amplifier BF is connected to the gates of the first PMOS transistor PM1 and the source follower PMOS transistor 302 to provide a bias voltage V bias , Because the first PMOS transistor PM1 and the source follower PMOS transistor 302 have the same aspect ratio and the same threshold voltage, the first PMOS transistor PM1 and the source follower PMOS transistor 302 form a mirror image Circuit. The first current source CS1 provides a working current for the first PMOS transistor PM1, so that the first PMOS transistor PM1 operates near a sub-threshold region (Sub-threshold Region). The gate source of the first PMOS transistor PM1 The voltage is close to its threshold voltage. Since the first PMOS transistor PM1 and the source follower PMOS transistor 302 are mirror circuits, the threshold voltages of the first PMOS transistor PM1 and the source follower PMOS transistor 302 are the same, and the source follower PMOS The gate-source voltage of the transistor 302 is also close to its threshold voltage, so the source follower PMOS transistor 302 also works in the sub-threshold region (Sub-threshold Region), when the voltage signal at the output of the low voltage regulator 301 appears During the pulse, the source PMOS transistor 302 can provide a pull-down current in a short time, so that the overshoot of the voltage signal is reduced.

[0039] In other embodiments of the present invention, the bias circuit further includes a first capacitor, the first terminal of the first capacitor is connected to the output terminal of the buffer amplifier, and the second terminal of the first capacitor is grounded. The function of the first capacitor is to make the gate voltage of the source follower PMOS transistor respond to the low dropout voltage regulator during the pull-down process of the source follower PMOS transistor Do not increase with the source voltage within time.

[0040] Please refer to Figure 4 , Figure 4 In this embodiment, the bias circuit 303 (please refer to image 3 ) Schematic diagram of the structure of the buffer amplifier BF. The buffer amplifier BF includes a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, and a fourth PMOS transistor PM5. NMOS transistor NM4 and second current source CS2. Wherein, the sources of the second PMOS transistor PM2, the third PMOS transistor PM3, the fourth PMOS transistor PM4, and the fifth PMOS transistor PM5 are connected to the power supply; the gate of the second PMOS transistor PM2 is connected to the gate of the third PMOS transistor PM3 The gate and the drain of the third PMOS transistor PM3, the drain of the second PMOS transistor PM2 is connected to the drain of the first NMOS transistor NM1 and the gate of the first NMOS transistor NM1; the fifth PMOS transistor PM5 The gate of the fourth PMOS transistor PM4 is connected to the drain of the fourth PMOS transistor PM4, the drain of the fifth PMOS transistor PM5 is connected to the drain of the fourth NMOS transistor NM4; the second NMOS transistor The drain of NM2 is connected to the drain of the third PMOS transistor PM3, the drain of the third NMOS transistor NM3 is connected to the drain of the fourth PMOS transistor PM4, and the source of the second NMOS transistor NM2 is connected to the The source of the three NMOS transistor NM3 is connected to the input terminal of the second current source CS2; the gate of the first NMOS transistor NM1 is connected to the gate of the fourth NMOS transistor NM4, and the source of the first NMOS transistor NM1 is The source of the fourth NMOS transistor NM4 and the output terminal of the second current source CS2 are grounded; the gate of the second NMOS transistor NM2 is the inverting input terminal INb of the buffer amplifier BF, and the third NMOS The gate of the transistor is the non-inverting input terminal INa of the buffer amplifier BF, and the drain of the fifth PMOS transistor PM5 and the drain of the fourth NMOS transistor NM4 are the output terminals of the buffer amplifier BF.

[0041] It should be noted that there are many specific implementations of the buffer amplifier. Figure 4 The above is disclosed only in preferred embodiments, and other buffer amplifiers that can realize the above functions can also be used in the bias circuit of the present invention.

[0042] Please continue to refer image 3 , The source of the source follower PMOS transistor 302 is connected to the output terminal of the low dropout regulator 301, and is used to input the voltage signal V out During overshoot, reduce the voltage overshoot.

[0043] Since the bias circuit 303 provides the bias voltage V for the source follower PMOS transistor 302 bias , The bias voltage V bias It is close to the threshold voltage of the source follower PMOS transistor 302, that is, the source follower PMOS transistor 302 works near the sub-threshold region, and the operating current of the source follower PMOS transistor 302 The voltage changes quickly with the source. The source of the source follower PMOS transistor 302 is connected to the output terminal of the low dropout regulator 301. When the load current of the low dropout regulator 301 suddenly decreases, the low dropout regulator 301 The voltage signal at the output end has an overshoot. At this time, the source voltage of the source follower PMOS transistor 302 rises, and the working current of the source follower PMOS transistor 302 rises rapidly in a short time. 301 output voltage signal V out Produces a pull-down effect, so that the voltage signal V out The voltage overshoot is reduced. In addition, since the source follower PMOS transistor 302 works near the sub-threshold region, especially when the bias voltage V bias When it is less than the threshold voltage of the source follower PMOS transistor 302, the drain current of the source follower PMOS transistor 302 is very small, and the static power consumption of the source follower PMOS transistor 302 is very low.

[0044] The number of the source follower PMOS transistors 302 is 10~10 5 One, the aspect ratio of the source follower PMOS transistor 302 is 5~1000. In this embodiment, the number of the source follower PMOS transistor 302 is 100, and the aspect ratio of the source follower PMOS transistor 302 is 20. The number of the source follower PMOS transistors 302 is larger, and the width and length are relatively high. When the source voltage of the source follower PMOS transistor 302 rises, a larger pull-down current can be generated, and the low voltage Voltage signal V at the output of the differential regulator 301 out The resulting pull-down effect is more obvious, and the voltage overshoot of the voltage signal Vout is smaller.

[0045] In other implementations of the present invention, a decoupling capacitor is further included. The first terminal of the decoupling capacitor is connected to the output terminal of the low dropout voltage regulator, and the second terminal of the decoupling capacitor is grounded. The decoupling capacitor can partially eliminate the influence of load changes on the output voltage signal of the low dropout regulator, for example, it can reduce the overshoot of the voltage signal when the load current decreases. However, the decoupling capacitor is usually small, and in other embodiments of the present invention, it is used in conjunction with the auxiliary circuit of the present invention.

[0046] The inventor of the present invention performed circuit simulation on the prior art low-dropout regulator and the low-dropout regulator with auxiliary circuit of the present invention to verify the effect of the present invention. Please refer to Figure 5 , Figure Ι shows the load current curve with time, Figure II Is the voltage signal change curve of the low dropout voltage regulator circuit in the prior art when the load current changes, Figure Ⅲ It is the voltage signal change curve of the low dropout voltage regulator circuit with auxiliary circuit according to the embodiment of the present invention when the load current changes. by Figure 5 It can be seen that when the load current is reduced from 20 mA to 0 mA, the voltage signal of the low dropout voltage regulator circuit in the prior art is overshooted from 1.8 volts to 3.1 volts. The voltage difference of the auxiliary circuit in the embodiment of the present invention is The voltage signal of the voltage regulator circuit is overshooted from 1.8 volts to 2.5 volts. Therefore, the overshoot amount of the voltage signal of the embodiment of the present invention is 0.7 volts less than the overshoot amount of 1.3 volts of the low dropout voltage regulator circuit in the prior art, which reduces the amount of voltage overshoot.

[0047] Although the present invention has been disclosed as above in preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can use the methods and techniques disclosed above to improve the technology of the present invention without departing from the spirit and scope of the present invention. Possible changes and modifications are made to the solution. Therefore, all simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the technical solution of the present invention belong to the protection of the technical solution of the present invention. range.