Layout graph correction method

A graphic correction and layout technology, applied in the semiconductor field, can solve problems such as difficult to control the feature size, shape, and position of through holes

Active Publication Date: 2013-05-15
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The problem to be solved by the present invention is that it is difficult to control the characteristic size, shape and position of the actually formed through holes in the layout pattern correction method of the prior art

Method used

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Embodiment Construction

[0032] In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0033] In the following description, specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways than those described here, and those skilled in the art can make similar extensions without departing from the connotation of the present invention. Accordingly, the present invention is not limited to the specific embodiments disclosed below.

[0034] At first several technical terms of the present invention are explained:

[0035] The target pattern is the pattern provided by the customer that is expected to be formed on the semiconductor substrate.

[0036] Layout pattern, the pattern expected to appear on the photoresist laye...

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Abstract

The invention discloses a layout graph correction method. The method comprises the following steps of: carrying out first segmentation on each side of a provided layout graph; carrying out first optical proximity correction on the segmented sides, which are subjected to the first segmentation, to obtain a layout middle graph, wherein a predetermined error exists between an actual graph simulated by the layout middle graph and a target graph; carrying out second segmentation on each side of the layout middle graph; and carrying out second optical proximity correction on the segmented sides, which are subjected to the second segmentation, to obtain a layout corrected graph. According to the technical scheme, the feature size, the shape and the position of the actually formed graph are easy to control.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a layout pattern correction method. Background technique [0002] In the semiconductor manufacturing process, the photolithography process plays a central role and is the most important process step in the production of integrated circuits. With the development of semiconductor manufacturing technology, the feature size is getting smaller and smaller, and the requirements for resolution in photolithography technology are getting higher and higher. Photolithography resolution refers to the minimum feature size (critical dimension, CD) that can be exposed on the surface of a silicon wafer by a photolithography machine, and is one of the important performance indicators in photolithography technology. [0003] In order to realize tiny CDs, it is necessary to focus finer images on the photoresist on the photoresist, and the photolithography resolution must be enhanced to manu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G03F1/36
Inventor 王伟斌王辉
Owner SEMICON MFG INT (SHANGHAI) CORP
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