Method for reducing feature size and semi-conductor etching method

Abstract

This invention relates to one method to contract characteristic sizes, which comprises the following steps: forming medium layer onto under layer; then forming pattern light anti-erosion layer on medium layer to expose part medium layer with first line width; then using pattern light anti-erosion layer as etching mask for etching to remove exposed medium layer with final width less than first line width.

Description

technical field [0001] The present invention relates to a semiconductor process, in particular to a method for shrinking a critical dimension (CD) and a semiconductor etching method. Background technique [0002] Metal-oxide semiconductor (MOS) transistors are very important electronic components in integrated circuits. Therefore, the electrical performance of metal-oxide semiconductor transistors will affect the quality of products. A general method to improve the electrical performance of metal-oxide-semiconductor transistors is to reduce the minimum line width (line width) of the gate to increase the working speed of the gate. Usually, when making the gate, it is necessary to form a hard mask layer on the polysilicon layer first, and then use a layer of patterned photoresist on the hard mask layer as an etching mask, and then process the hard mask layer Etching, and finally etching the polysilicon layer using the hard mask layer as a mask to form a gate. However, this m...

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Problems solved by technology

[0005] However, the process of trimming the photoresist is not stable, and it is easy to cause insufficient thickness of the remaining photoresist layer due to too fast etching, and cause necking or widening phenomenon, and photoresist The uneven shape of the etchant makes the sidewall of the gate rough or linearly distorted, which affects the shape of the formed gate and the consistency of the feature size

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