Photolithography method capable of preventing ground silicon dust from polluting wafers

Abstract

The invention discloses a photolithography method capable of preventing ground silicon dust from polluting wafers. The exposure condition of an invalid region at the wafer gap side of a photoresist polyimide layer is set as non-exposure, so that photoresist can fully fill the interspace at the wafer gap side so as to enhance the combination of a front film and a scribing groove of a wafer. In the method, the exposure condition of the polyimide layer is optimized, the exposure condition of the invalid region at the wafer gap side is changed to be non-exposure, and the photoresist in the wafer is retained for fully filling the interspace of the scribing groove, so that the combination of the scribing groove and the grinding film is improved, and the silicon dust is prevented from penetrating from the interspace and polluting the wafer.

Description

technical field [0001] The invention belongs to the manufacturing process of semiconductor integrated circuits, and relates to a photolithography process, in particular to a method for optimizing the exposure conditions of photoresist in the manufacturing process of semiconductor integrated circuits, and in particular to a photolithography method for preventing ground silicon chips from contaminating wafers. process method. Background technique [0002] FIG. 1 is a schematic diagram of a wafer after exposure under conventional photolithography conditions. As shown in Figure 1, since the existing lithography conditions do not specify that the invalid area on the wafer notch (wafer notch) side is not exposed, the photoresist in this area is removed after exposure, resulting in a void 3 on the notch side (see Figure 1A with Figure 1B ), the scribing groove in the gap 3 on the side of the notch and the front film 1 during grinding are usually not well bonded, resulting in the...

AI Technical Summary

Problems solved by technology

As shown in Figure 1, since the existing lithography conditions do not specify that the invalid area on the wafer notch (wafer notch) side is not exposed, the photoresist in this area is removed after exposure, resulting in a void 3 on the notch side (see Figure 1A and Figure 1B ), the scribing groove in the gap 3 on the side of the notch and the front film 1 during grinding are usually not well bonded, resulting in the silicon chips generated during grinding can easily escape from the groove of the dicing groove (such as Figure 1C As shown, the depth of the dicing groove is about 30 microns), that is, it penetrates into the wafer 2 from the gap on the notch side, contaminates the surface of the wafer 2, and reduces the yield of the device

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