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Method, device and system of testing of chip frequency

A test method and chip technology, applied in the electrical field, can solve problems such as increased chip production costs, high cost, and complicated test methods, and achieve the effects of reducing production costs, improving reliability, and reducing the probability of mistesting

Inactive Publication Date: 2013-05-22
HISILICON TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The inventor found in the process of realizing the present invention that in the traditional method, the evaluation and grouping of the chip frequency are completed by testing the chips on the board-level system, but the test method based on the board-level system is more complicated, and in the process of testing Human intervention is required in the process, which reduces the reliability of test results
In addition, when this method is used for large-scale chip frequency testing, the cost is very high, thereby increasing the production cost of the chip

Method used

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  • Method, device and system of testing of chip frequency
  • Method, device and system of testing of chip frequency

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0018] Embodiments of the present invention provide a method for testing chip frequency, such as figure 1 As shown, the method includes:

[0019] Step S101, acquiring each functional test vector corresponding to each test path of the chip, where the test path includes a critical path and an effective path;

[0020] A basic definition of a test vector is that a test vector is logic 1 and logic 0 data applied to a device pin every clock cycle for testing or manipulation. Logic 1s and 0s are represented by waveforms with timing characteristics and level characteristics, related to waveform shape, pulse width, pulse edge or slope, and position of rising and falling edges. In automated test language, these waveforms are represented by this formatted description of the rising edge, falling edge, and setup and hold time requirements of the device pins.

[0021] According to the different test vectors, it can be divided into functional test vectors and structural test vectors.

[0...

Embodiment 2

[0032] Embodiments of the present invention provide a method for testing chip frequency, such as figure 1 As shown, the method includes:

[0033] Step S101, acquiring each functional test vector corresponding to each test path of the chip, where the test path includes a critical path and an effective path;

[0034] A basic definition of a test vector is that a test vector is logic 1 and logic 0 data applied to a device pin every clock cycle for testing or manipulation. Logic 1s and 0s are represented by waveforms with timing characteristics and level characteristics, related to waveform shape, pulse width, pulse edge or slope, and position of rising and falling edges. In automated test language, these waveforms are represented by this formatted description of the rising edge, falling edge, and setup and hold time requirements of the device pins.

[0035] According to the different test vectors, it can be divided into functional test vectors and structural test vectors.

[0...

Embodiment 3

[0068] The embodiment of the present invention provides a chip frequency test device, such as Figure 4 As shown, the device includes:

[0069] an acquisition unit, which acquires each functional test vector corresponding to each test path of the chip, where the test path includes a critical path and an effective path;

[0070] A basic definition of a test vector is that a test vector is logic 1 and logic 0 data applied to a device pin every clock cycle for testing or manipulation. Logic 1s and 0s are represented by waveforms with timing characteristics and level characteristics, related to waveform shape, pulse width, pulse edge or slope, and position of rising and falling edges. In automated test language, these waveforms are represented by this formatted description of the rising edge, falling edge, and setup and hold time requirements of the device pins.

[0071] According to the different test vectors, it can be divided into functional test vectors and structural test v...

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Abstract

The invention discloses a method, a device and a system of testing of chip frequency, and relates to the field of electricity. The method, the device and the system of the testing of the chip frequency are capable of improving the chip frequency and reliability of a testing result, and reducing production cost of a chip. The method of the testing of the chip frequency comprises: acquiring test vectors of each function corresponded by each effective path of the chip; converting formats of the vectors of the function testing into the formats which an automatic testing appliance supports; each testing vector of the functions after conversion is stored into a memory of the chip to enable the automatic testing appliance to run the testing vectors of each function stored inside the memory of the chip, and to acquire the highest frequency of each testing vector of functions during the running of the chip respectively.

Description

technical field [0001] The invention relates to the field of electricity, in particular to a method, device and system for testing chip frequency. Background technique [0002] The frequency test of the chip refers to the process of classifying chip products according to the highest frequency when the chip itself functions normally. With the development of deep sub-nanometer manufacturing process, the deviation of chip performance caused by manufacturing defects is increasing. Generally speaking, after a high-performance chip is produced, before it reaches the user, the frequency of the chip needs to be tested, that is, the chips are evaluated and grouped according to different chip functional frequencies, and the price of the chip is divided: frequency If the frequency is high, the market price is also high; if the frequency is low, the market price is also lower. To sum up, the frequency test will calibrate the chips with different operating frequencies, and select chips...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R23/02
Inventor 郑虹白利李国栋
Owner HISILICON TECH
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