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Phase-locked loop circuit and working method thereof

A working method and phase-locked loop technology, applied in the field of communication, can solve problems such as poor reception performance, and achieve the effect of minimizing the circuit area

Active Publication Date: 2013-06-26
NATIONZ TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] At present, PLL frequency synthesizers can be divided into integer-N frequency division and fractional frequency division according to whether the frequency division coefficient of the frequency divider changes dynamically and randomly. The integer frequency division PLL frequency synthesizer has a simple structure and open-loop transmission The performance is better, but the receiving performance is poor. The fractional frequency division PLL frequency synthesizer has better receiving performance, but a complex correction circuit needs to be added for closed-loop transmission.

Method used

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  • Phase-locked loop circuit and working method thereof
  • Phase-locked loop circuit and working method thereof
  • Phase-locked loop circuit and working method thereof

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Embodiment Construction

[0014] figure 1 It is a schematic diagram of a phase-locked loop circuit according to an embodiment of the present invention, please refer to figure 1 :

[0015] A phase-locked loop circuit includes a phase-locked loop core unit 1 and a phase-locked loop control unit 2, the phase-locked loop core unit 1 can include an integer frequency division module and a fractional frequency division module, and the phase-locked loop control unit 2 can include a channel selection module , frequency division reference frequency selection module and parameter setting and adjustment module. Loop mode output signal; when the PLL circuit is in the receiving state, the PLL core unit 1 outputs the signal through the fractional frequency division closed-loop mode under the control of the three modules of the PLL control unit 2 .

[0016] Taking the PLL frequency synthesizer applied in the radio frequency transceiver as an example, a hybrid PLL frequency synthesizer is proposed below. The phase-l...

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Abstract

The invention discloses a phase-locked loop circuit. The phase-locked loop circuit comprises a phase-locked loop core unit and a phase-locked loop control unit, wherein when the phase-locked loop circuit is in a transmission state, the phase-locked loop core unit outputs a signal through a integer frequency division open loop mode under the control of the phase-locked loop control unit; and when the phase-locked loop circuit is in a reception state, the phase-locked loop core unit outputs a signal through a fractional frequency division closed loop mode under the control of the phase-locked loop control unit. Through the technical scheme of the invention, a more complete phase-locked loop circuit is provided.

Description

technical field [0001] The invention relates to the communication field, in particular to a phase-locked loop circuit and a working method thereof. Background technique [0002] The phase-locked loop (PLL, Phase-Locked Loop) frequency synthesizer is one of the core components of the radio frequency transceiver. When the radio frequency transceiver is in the transmitting state, the PLL frequency synthesizer modulates the transmitted data to the carrier frequency; in the receiving state , the PLL frequency synthesizer generates a local oscillator signal, which is used for mixing with the received signal to obtain a demodulated signal. [0003] At present, PLL frequency synthesizers can be divided into integer-N frequency division and fractional frequency division according to whether the frequency division coefficient of the frequency divider changes dynamically and randomly. The integer frequency division PLL frequency synthesizer has a simple structure and open-loop transmis...

Claims

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Application Information

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IPC IPC(8): H03L7/099H03L7/18
Inventor 唐佳捷史爱焕
Owner NATIONZ TECH INC