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Thin film transistor (TFT) array substrate, manufacturing method and display device of TFT array substrate

A manufacturing method and array substrate technology, applied in the field of TFT array substrates, manufacturing methods of TFT array substrates and display devices, can solve problems such as excessive use of mask plates, and achieve the effect of reducing use

Active Publication Date: 2015-04-08
BEIJING BOE OPTOELECTRONCIS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0017] The purpose of the present invention is to provide a TFT array substrate, a method for manufacturing a TFT array substrate and a display device, so as to solve the problem of excessive use of mask plates in the prior art

Method used

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  • Thin film transistor (TFT) array substrate, manufacturing method and display device of TFT array substrate
  • Thin film transistor (TFT) array substrate, manufacturing method and display device of TFT array substrate
  • Thin film transistor (TFT) array substrate, manufacturing method and display device of TFT array substrate

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0039] In the method for manufacturing a TFT array substrate provided in Embodiment 1 of the present invention, firstly, a gate electrode 1 and a gate line 2 are formed on the substrate, and a gate insulating layer 3 is formed over the gate line 2 and the gate electrode 1; Deposit a semiconductor layer and a metal layer, and carry out a patterning process on the semiconductor layer and the metal layer using the same mask to form an active layer 4, a source electrode 51, and a drain electrode 52 above the gate electrode 1, and to form an active layer 4 above the gate electrode 1 and a drain electrode 52 above the gate line 2 Cover the signal line 5 of the residual semiconductor layer 401; then perform a via process on the signal line 5, the residual semiconductor layer 401 located below the signal line, and the gate insulating layer 3 to form a via hole 11, and expose the signal line on the side wall of the via hole 11 The side section of the line 5 and the side section of the s...

Embodiment 2

[0042] Embodiment 2 of the present invention will describe the manufacturing method of the above-mentioned TFT array substrate in Embodiment 1 in detail in combination with practical applications. Of course, it is not limited thereto. The manufacturing process of the TFT array substrate in Embodiment 2 of the present invention is as follows image 3 shown, including:

[0043] Step S301 : using a first mask to perform a first patterning process to form gate electrodes 1 and gate lines 2 .

[0044] Specifically, in the embodiment of the present invention, after the gate metal film is deposited on the substrate by magnetron sputtering or thermal evaporation, the first patterning process can be performed using the first mask to form the gate electrode 1 and the gate line 2, Such as Figure 4A shown.

[0045] Step S302: On the basis of the patterning process completed in step S301, a gate insulating layer, a semiconductor layer and a metal layer are sequentially deposited.

[00...

Embodiment 3

[0063] Embodiment 3 of the present invention also provides a TFT array substrate manufactured by applying the manufacturing method of the above embodiment, the TFT array substrate includes: gate lines 2 and gate electrodes 1 formed on the substrate; covering gate lines 2 and gate electrodes 1 The gate insulating layer 3; the active layer 4, the source electrode 51 and the drain electrode 52 formed on the gate insulating layer 3 and positioned above the gate electrode 2; the residual semiconductor layer 401 formed on the gate insulating layer 3 and positioned above the gate line , and the signal line 5 covering the residual semiconductor layer 401; and the signal line 5, the semiconductor layer 401, and the gate insulating layer 3 also have a side wall exposing the side section of the signal line 5 and a side section of the semiconductor layer 401, and the bottom surface exposes the gate line 2 The via hole 11 on the surface; the overlapping conductive layer 12 for electrically ...

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Abstract

Disclosed are an array substrate, a method for manufacturing an array substrate, and a display device. The method for manufacturing an array substrate comprises: forming a gate line and a gate electrode on a substrate; forming a gate insulation layer above the gate line and the gate electrode; depositing a semiconductor layer and a metal layer in sequence above the gate insulation layer, using a patterning process to form an active layer, a source electrode and a drain electrode which are located above the gate electrode, a residual semiconductor layer located above the gate line and a signal line covering the residual semiconductor layer; performing a patterning process on the signal line, the residual semiconductor layer located below the signal line and the gate insulation layer to form a via hole, so as to enable the surface of the gate line, the side section of the signal line, the side section of the residual semiconductor layer and the side section of the gate insulation layer to be exposed through the via hole; and forming a lapping conducting layer at the location of the via hole, so as to enable the signal line to be electrically connected to the gate line.

Description

technical field [0001] The invention relates to the field of display manufacturing, in particular to a TFT array substrate, a manufacturing method of the TFT array substrate and a display device. Background technique [0002] The main structure of a Thin Film Transistor Liquid Crystal Display (TFT-LCD for short) includes an array substrate and a color filter substrate that are boxed together with liquid crystal sandwiched between them. The array substrate is formed with gate lines, data lines and Thin film transistors and pixel electrodes arranged in a matrix. [0003] Such as figure 1 Shown is the flow chart of the existing TFT array substrate fabrication, including: [0004] Step S101 : forming gate electrodes 1 and gate lines 2 . [0005] Deposit gate metal material on the substrate, and use mask plate etching to form gate electrode 1 and gate line 2, such as Figure 2A shown. [0006] Step S102 : forming a gate insulating layer 3 and an active layer 4 . [0007] A ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/77H01L27/12G02F1/1368
CPCH01L27/1259H01L27/124H01L27/127
Inventor 郭建
Owner BEIJING BOE OPTOELECTRONCIS TECH CO LTD