Bump structural designs to minimize package defects
A chip package, copper pillar bump technology, applied in the direction of electrical components, electrical solid devices, semiconductor devices, etc.
Active Publication Date: 2013-07-31
TAIWAN SEMICON MFG CO LTD
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- Abstract
- Description
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- Application Information
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Problems solved by technology
There are many challenges in the chip packaging process
Method used
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[0035] The making and using of embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be implemented in a wide variety of specific contexts. The specific embodiments discussed are illustrative only, and do not limit the scope of the disclosure.
[0036] Figure 1A is a bump structure 100 with a substrate 110 according to some embodiments. The substrate 110 may be a semiconductor substrate, such as a bulk silicon substrate, but the substrate may include other semiconductor materials, such as group III, group IV, and / or group V elements. Semiconductor devices 114 (eg, transistors) may be formed on the surface of the substrate 110 . Substrate 110 may include silicon, gallium arsenide, silicon-on-insulator (“SOI”), or other similar materials. The substrate 110 may also include: passive devices, such as resistors, capacitors, inductors, etc.; or active device...
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The mechanisms for forming bump structures enable forming bump structures between a chip and a substrate eliminating or reducing the risk of solder shorting, flux residue and voids in underfill. A lower limit can be established for a cc ratio, defined by dividing the total height of copper posts in a bonded bump structure divided by the standoff of the bonded bump structure, to avoid shorting. A lower limit may also be established for standoff the chip package to avoid flux residue and underfill void formation. Further, aspect ratio of a copper post bump has a lower limit to avoid insufficient standoff and a higher limit due to manufacturing process limitation. By following proper bump design and process guidelines, yield and reliability of chip packages may be increases.
Description
technical field [0001] The present invention relates generally to the field of semiconductor technology, and more particularly, to chip packages and methods of forming the same. Background technique [0002] The fabrication of modern circuits typically involves many process operations. Integrated circuits are first fabricated on a semiconductor wafer containing a plurality of replicated semiconductor chips, each semiconductor chip including an integrated circuit. Then, the wafer is diced into semiconductor chips and the semiconductor chips are packaged. The packaging process has two main purposes: to protect the delicate semiconductor chips, and to connect the internal integrated circuits to external connections. [0003] In the packaging of integrated circuit (IC) chips, solder bonding is a method of bonding the IC chip to a packaging substrate, which may or may not include the integrated circuit and / or other passive components. The package substrate may also include thr...
Claims
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IPC IPC(8): H01L23/498H01L21/48H01L21/60
CPCH01L24/83H01L2224/05639H01L23/49894H01L2224/8191H01L2224/05624H01L21/563H01L24/02H01L2224/1601H01L24/05H01L2224/13116H01L2224/11849H01L2224/05008H01L2224/05181H01L2224/13083H01L2224/16238H01L2224/83104H01L2224/13113H01L2224/05644H01L2224/83855H01L24/13H01L21/56H01L24/81H01L23/49816H01L2224/73204H01L2224/13147H01L2224/13155H01L2224/05187H01L2224/81815H01L2224/81011H01L2224/13139H01L24/16H01L2224/05166H01L2224/0239H01L2224/13024H01L2224/05647H01L2224/13005H01L2224/81193H01L24/11H01L2224/81911H01L2224/16227H01L23/3171H01L2224/13111H01L2224/16225H01L2924/381H01L2924/3841H01L2224/0401H01L23/3192H01L2224/05572H01L2924/01029H01L2924/01047H01L2924/01079H01L2924/01028H01L2924/01074H01L2924/04941H01L2924/04953H01L2924/00014H01L2224/13012H01L2224/13023H01L2224/13082H01L2224/81801
Inventor 林俊成黄震麟
Owner TAIWAN SEMICON MFG CO LTD