Memory and storage array thereof, access control method, and access control circuit

A storage array and access control technology, which is applied in the field of memory and its storage array, access control circuit, can solve problems such as occupancy, unfavorable chip size reduction, etc., and achieve the goal of improving storage efficiency, reducing spacing distance, and increasing byte unit density Effect

Active Publication Date: 2013-08-07
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] However, each control switch in the switch array needs to occupy a certain chip area, which leads to the distance between each byte unit of the memory (suc

Method used

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  • Memory and storage array thereof, access control method, and access control circuit
  • Memory and storage array thereof, access control method, and access control circuit
  • Memory and storage array thereof, access control method, and access control circuit

Examples

Experimental program
Comparison scheme
Effect test

Example Embodiment

[0051] Example 1

[0052] This embodiment provides a storage array, such as image 3 shown, including:

[0053] A plurality of byte units, where the byte unit includes a plurality of storage units.

[0054] The storage array described in this embodiment includes byte units arranged in a matrix of rows and columns. Here, rows and columns are relative concepts and can be interchanged. like image 3 Among them, let the byte unit composed of storage units m11, m12, ..., m17, m18 be the target byte unit, and the word adjacent to the target byte unit on the same row is composed of storage units m19, m110, ... Section unit, adjacent on the same column as the target byte unit is a byte unit composed of storage units m21, m22, ..., m27, m28, and the present embodiment assumes that the target byte unit is adjacent on the same row The byte unit is a row byte unit, and the byte unit adjacent to the target byte unit on the same column is a column byte unit.

[0055] A plurality of sto...

Example Embodiment

[0063] Example 2

[0064] Corresponding to the storage array in Embodiment 1, this embodiment provides an access control method for a storage array, including performing the following steps: Figure 5 The steps shown to erase the data in each memory location in the target byte location:

[0065] In step S101, a first word line voltage is applied to word lines connected to memory cells in a target byte unit, and other word lines are set to zero.

[0066] The value range of the shown first word line voltage may be 6V-9V, combined with figure 1 , the first word line voltage loaded on the first word line charges the middle electrode of each memory cell in the target byte unit to a high driving voltage, so that the middle electrode 119 and the floating gate (the first floating gate 105 or the second floating gate 113 ), a high electric field is generated, and the high electric field can move electrons out of the first floating gate 105 corresponding to the first storage bit or th...

Example Embodiment

[0083] Example 3

[0084] A kind of access control circuit corresponding to the storage array of embodiment 2, such as Figure 4 shown. Figure 4 It is a structural schematic diagram of a memory array including several memory blocks and its access control circuit, including memory blocks 11, 21, . . . , 1n, 2n, . . . arranged in a matrix. The structures of each storage block and its access control circuit are similar (the following examples all take the storage block 11 as an example).

[0085] The access control circuit of the storage array in this embodiment includes:

[0086] The word line control unit 1 is used to load the first word line voltage to the word line connected to each memory cell of the target byte unit when performing data erasing on each memory cell in the target byte unit, and to other word lines Zero. The word line control unit 1 includes a plurality of word line control switches respectively connected to corresponding word lines, see Figure 4 , the ...

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Abstract

The invention relates to a memory and a storage array thereof, an access control method, and an access control circuit. The storage array comprises a plurality of byte units, a plurality of bit lines, control grid lines and word lines, wherein control grids of first storage bits and second storage bits of various storage units in the same byte unit share the one control grid line, and middle electrodes in the same row of the storage units share the one word line. The storage array access control method comprises performing the following steps to erase data in various storage units of the target byte, wherein the steps comprise: loading a first control voltage on the control grid lines connected with various storage units in the target byte unit, and loading a second control voltage on other control grid lines, wherein the first control voltage is less than zero potential, and the second control voltage is higher than zero potential; and respectively setting the two bit lines connected with various storage units in the target byte unit as zero, and loading a first bit line voltage on other bit lines. With the technical scheme, separation distances between various byte units of the memory can be reduced.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a memory and its storage array, an access control method and an access control circuit. Background technique [0002] Electrically Erasable Programmable Read-Only Memory, also known as EEPROM memory (EEPROM, Electrically Erasable Programmable Read-Only Memory) is a semiconductor memory that does not lose data after power failure. EEPROM memory can erase at least one byte (Byte) at a time. [0003] EEPROM memory consists of EEPROM memory cells such as figure 1 A kind of EEPROM storage cell shown, comprises two symmetrically distributed first storage positions and second storage positions; wherein, the first storage position comprises the first bit line electrode 101, the first control gate 103, the first floating gate 105 and the first channel region 107 below the first floating gate 105; the second storage bit includes a second bit line electrode 109, a second control...

Claims

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Application Information

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IPC IPC(8): G11C16/06G11C16/02
Inventor 杨光军顾靖
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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