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A mos device for integrated circuit chip esd protection

A MOS device and integrated circuit technology, applied in the electronic field, can solve the problems of increased device production cost, increased chip area, increased device size, etc., and achieves increased substrate resistance, increased substrate resistance, and improved secondary breakdown. effect of current

Inactive Publication Date: 2015-07-29
UNIV OF ELECTRONICS SCI & TECH OF CHINA +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this method will lead to an increase in the size of the device and an increase in the chip area, which will lead to an increase in the production cost of the device

Method used

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  • A mos device for integrated circuit chip esd protection
  • A mos device for integrated circuit chip esd protection
  • A mos device for integrated circuit chip esd protection

Examples

Experimental program
Comparison scheme
Effect test

specific Embodiment approach 1

[0020] An NMOS device for ESD protection of integrated circuit chips, such as Figure 5 As shown, it includes a P-type semiconductor substrate, a P-type semiconductor source-substrate contact region, an N-type semiconductor source region, and an N-type semiconductor drain region; the P-type semiconductor source-substrate contact region, the N-type semiconductor source region and the The N-type semiconductor drain regions are all located on the surface of the P-type semiconductor substrate, wherein the P-type source end substrate contact region and the N-type semiconductor source region are connected to the source metal, and the N-type semiconductor drain region is connected to the drain metal; the N-type semiconductor drain region is connected to the drain metal; The semiconductor source region is located between the contact region of the P-type semiconductor source end substrate and the N-type semiconductor drain region, and the surface of the P-type semiconductor substrate be...

specific Embodiment approach 2

[0022] A PMOS device for ESD protection of integrated circuit chips, such as Image 6 As shown, it includes an N-type semiconductor substrate, an N-type semiconductor source-substrate contact region, a P-type semiconductor source region, and an N-type semiconductor drain region; the N-type semiconductor source-substrate contact region, the P-type semiconductor source region and the The P-type semiconductor drain regions are all located on the surface of the N-type semiconductor substrate, wherein the N-type source end substrate contact region and the P-type semiconductor source region are connected to the source metal, and the P-type semiconductor drain region is connected to the drain metal; the P-type semiconductor drain region is connected to the drain metal; The semiconductor source region is located between the contact region of the N-type semiconductor source end substrate and the P-type semiconductor drain region, and the surface of the N-type semiconductor substrate bet...

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Abstract

The invention relates to an MOS (Metal Oxide Semiconductor) device for ESD (Electrostatic Discharge) protection of an integrated circuit chip, belonging to the technical field of electronics. On the premise that the size of the device is not increased and more chip area is not required to be consumed, substrate resistance between a source region and a substrate contact region is increased by adding a plurality of strip-shaped well regions which are in parallel with the transverse direction of the device in a substrate region below a position between the source region and the substrate contact region, so that the ESD resisting ability of the device is improved; besides, the size of the substrate resistance of the device can be adjusted and the problem of poor starting uniformity of the device can be solved by adjusting the quantity and the width of the strip-shaped well regions and the mutual distances among the strip-shaped well regions, so that the secondary breakdown current of the device is further improved; meanwhile, the manufacturing process of the MOS device is compatible with the standard CMOS process. In conclusion, the MOS device for the ESD protection of the integrated circuit chip provided by the invention has stronger ESD resisting ability due to the increase of the substrate resistance and the production cost of the device is not increased because the size of the device is not increased.

Description

technical field [0001] The invention belongs to the field of electronic technology, and relates to MOS devices, in particular to a MOS device used for electrostatic discharge (ElectroStatic Discharge, ESD for short) protection of semiconductor integrated circuit chips. Background technique [0002] In the process of IC chip production, packaging and testing, electrostatic discharge is common as an unavoidable natural phenomenon. With the reduction of the feature size of integrated circuits and the development of various advanced processes, it is more and more common for integrated circuit chips to be damaged by ESD, which seriously affects the yield of integrated circuits in chip production. Manufacturers are paying more and more attention to the design of the anti-static discharge capability of chip integrated circuits. [0003] figure 1 and figure 2 They are a top view and a cross-sectional view of an ordinary NMOS transistor, respectively. As a common device in the C...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/06
Inventor 张波曲黎明樊航蒋苓利盛玉荣
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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