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44results about How to "Reduce effective width" patented technology

Super junction semiconductor device manufacturing method capable of improving avalanche capacity

The invention relates to a super junction semiconductor device manufacturing method capable of improving the avalanche capacity. On-resistance is increased correspondingly due to transverse diffusion caused by the traditional high dosage concentration of a column P, and puncture voltage is reduced due to electric charge unbalance of the column P and a column N. According to the method, the epitaxy technology is utilized to form an N-type epitaxy layer; a P-type and N-type epitaxy layer is formed by injecting boron ions; the injection amount of the boron ions increases gradually, and the boron ions are pushed under the high temperature to form a P-type and N-type alternant epitaxy layer; a Pbody area is formed by injecting the boron ions; a polycrystalline silicon gate electrode is formed by etching polycrystalline silicon through the dry method; an N+ source area is formed by injecting arsenic ions; a layer of aluminum is deposited on the upper surface of a whole device, a source metal electrode is formed by etching the aluminum, and a drain electrode is formed on the back face through metallization. According to the super junction semiconductor device obtained through the method, the avalanche capacity of the super junction semiconductor device is improved, and at the same time, on-resistance is reduced.
Owner:XIAN LONTEN RENEWABLE ENERGY TECH +1

A mos device for integrated circuit chip esd protection

InactiveCN103280458BImprove turn-on uniformityIncrease the secondary breakdown currentSemiconductor devicesElectrical resistance and conductancePower flow
The invention relates to an MOS (Metal Oxide Semiconductor) device for ESD (Electrostatic Discharge) protection of an integrated circuit chip, belonging to the technical field of electronics. On the premise that the size of the device is not increased and more chip area is not required to be consumed, substrate resistance between a source region and a substrate contact region is increased by adding a plurality of strip-shaped well regions which are in parallel with the transverse direction of the device in a substrate region below a position between the source region and the substrate contact region, so that the ESD resisting ability of the device is improved; besides, the size of the substrate resistance of the device can be adjusted and the problem of poor starting uniformity of the device can be solved by adjusting the quantity and the width of the strip-shaped well regions and the mutual distances among the strip-shaped well regions, so that the secondary breakdown current of the device is further improved; meanwhile, the manufacturing process of the MOS device is compatible with the standard CMOS process. In conclusion, the MOS device for the ESD protection of the integrated circuit chip provided by the invention has stronger ESD resisting ability due to the increase of the substrate resistance and the production cost of the device is not increased because the size of the device is not increased.
Owner:UNIV OF ELECTRONICS SCI & TECH OF CHINA +1

Current sampling circuit achieved through LDMOS devices

The invention discloses a current sampling circuit achieved through LDMOS devices. A sampling tube and a sampled tube are both the LDMOS devices, the sampling tube is arranged in the middle area of the sampled tube, and the effective width of a source region of the sampling tube is determined by the contact width of an N+ region of the resource region and a grid electrode. A voltage resisting buffer layer is arranged in a drift region of a drain region of the sampling tube, the voltage resisting buffer layer can define the effective drain region drift region aligned to the effective part of the source region, and meanwhile the surrounding range of the whole drain region drift region is not reduced. The sampling ratio of the circuit can be improved by reducing the effective width of the source region, and due to the fact that the effective drain region drift region is aligned to the N+ region of the source region, parasitic resistance between the source region and the drain region of the sampling tube and parasitic resistance between the source region and the drain region of the sampled tube are in proportion, and the stability of the sampling ratio can be improved. The matching degree and stability of the sampling tube and the sampled tube can be improved, the occupied area of the circuit can be reduced, and the integration degree can be improved.
Owner:SHANGHAI HUAHONG GRACE SEMICON MFG CORP

MOS (Metal Oxide Semiconductor) device for ESD (Electrostatic Discharge) protection of integrated circuit chip

InactiveCN103280458AImprove turn-on uniformityIncrease the secondary breakdown currentSemiconductor devicesElectrical resistance and conductanceEngineering
The invention relates to an MOS (Metal Oxide Semiconductor) device for ESD (Electrostatic Discharge) protection of an integrated circuit chip, belonging to the technical field of electronics. On the premise that the size of the device is not increased and more chip area is not required to be consumed, substrate resistance between a source region and a substrate contact region is increased by adding a plurality of strip-shaped well regions which are in parallel with the transverse direction of the device in a substrate region below a position between the source region and the substrate contact region, so that the ESD resisting ability of the device is improved; besides, the size of the substrate resistance of the device can be adjusted and the problem of poor starting uniformity of the device can be solved by adjusting the quantity and the width of the strip-shaped well regions and the mutual distances among the strip-shaped well regions, so that the secondary breakdown current of the device is further improved; meanwhile, the manufacturing process of the MOS device is compatible with the standard CMOS process. In conclusion, the MOS device for the ESD protection of the integrated circuit chip provided by the invention has stronger ESD resisting ability due to the increase of the substrate resistance and the production cost of the device is not increased because the size of the device is not increased.
Owner:UNIV OF ELECTRONICS SCI & TECH OF CHINA +1

High-threshold power semiconductor device and manufacturing method thereof

ActiveCN112164725AReduce the effective channel widthGood uniformity over a large areaSemiconductor/solid-state device manufacturingSemiconductor devicesCapacitancePower semiconductor device
The invention discloses a high-threshold power semiconductor device and a manufacturing method thereof. The high-threshold power semiconductor device sequentially comprises a drain metal electrode, asubstrate, a buffer layer and a drift region from bottom to top, and also comprises: a composite column body on the drift region, formed by a drift region protrusion, a columnar p region and a columnar n region, and a channel layer, a passivation layer, a dielectric layer, a heavily doped semiconductor layer, a gate metal electrode and a source metal electrode. The composite column body is formedby sequentially depositing a p-type semiconductor layer and an n-type semiconductor layer on the drift region and then etching the p-type semiconductor layer and the n-type semiconductor layer; wherein the channel layer and the passivation layer are formed by deposition in sequence. Therefore, the device is divided into a cellular region and a terminal region. The dielectric layer, the heavily doped semiconductor layer, the gate metal electrode and the source metal electrode only exist in the cellular region, and the passivation layer of the terminal region extends upwards and wraps the outerside of the channel layer. The structure can improve the threshold voltage of the device, improve the blocking characteristic of the device, and reduce the gate capacitance.
Owner:SOUTHEAST UNIV

Preparation method of super junction semiconductor device capable of improving avalanche capability

The invention relates to a super junction semiconductor device manufacturing method capable of improving the avalanche capacity. On-resistance is increased correspondingly due to transverse diffusion caused by the traditional high dosage concentration of a column P, and puncture voltage is reduced due to electric charge unbalance of the column P and a column N. According to the method, the epitaxy technology is utilized to form an N-type epitaxy layer; a P-type and N-type epitaxy layer is formed by injecting boron ions; the injection amount of the boron ions increases gradually, and the boron ions are pushed under the high temperature to form a P-type and N-type alternant epitaxy layer; a Pbody area is formed by injecting the boron ions; a polycrystalline silicon gate electrode is formed by etching polycrystalline silicon through the dry method; an N+ source area is formed by injecting arsenic ions; a layer of aluminum is deposited on the upper surface of a whole device, a source metal electrode is formed by etching the aluminum, and a drain electrode is formed on the back face through metallization. According to the super junction semiconductor device obtained through the method, the avalanche capacity of the super junction semiconductor device is improved, and at the same time, on-resistance is reduced.
Owner:XIAN LONTEN RENEWABLE ENERGY TECH +1
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