Area-Efficient Single-legged SOI MOSFET structure immune to single-event-effects and bipolar latch-up

Abstract

New device structure for single-legged Silicon-On-Insulator Metal-Oxide-Semiconductor (SOI MOS) transistor is presented. This new structure imposes a hard barrier for an Impact-Ionization current and for transients due to Single-Event-Effects (SEE's) in Body to laterally conduct (or diffuse) to the Source through the Body / Source junction. It forces these currents to conduct instead to the Source through an alternate path made of highly conductive Silicide. This alternate path effectively suppresses the latch-up of the built-in parasitic Bipolar structure without necessitating the incorporation of Body-Tied-Source (BTS) implant into the device structure that increases the total device periphery without correspondingly scaling its device current.

Description

BACKGROUND OF THE INVENTION[0001]There are two primary approaches to the design of large-periphery Metal-Oxide-Semiconductor (MOS) Transistors; one relies on cascading (or arraying) column of multi-Legs (or multi-Fingers) Gates in parallel to enable delivering the required high output current. The other utilizes one single-legged device having sufficiently large Gate width that enables it to deliver same or similar amount of output current. Major advantage of the former approach is that it ensures a desired “Square-like” footprint for any particular large-periphery Transistor Layout. This provides more ease and flexibility in designing and laying-out such Large-periphery Transistors in any given Integrated-Circuit (IC). It can also reduce the device Gate Resistance, and hence it can boost the device power-gain and Bandwidth. The drawback can come however from an excessive increase of the Capacitive parasitic's with the increase of number of Legs (due to a corresponding increase from...

AI Technical Summary

Benefits of technology

The invention provides a new structure for a MOS device that reduces the effects of "bipolar latch-up" and is more efficient in its use of space. It achieves this by trapping the impact-ionization current in a highly doped pocket that interfaces with the source and device body, instead of diverting it to the base. This design has the same dopant type as the device body and uses a high conductive path to effectively divert the current away from the lateral junction without increasing the effective width of the transistor. It can be used for both FD-SOI and PD-SOI MOS devices, and can be further enhanced with the use of additional interconnects for even higher electrical conductance.

Problems solved by technology

This design can still effectively divert impact-ionization current away from the lateral Body-to-Source Junction and does not reduce the “effective” Width of the Transistor.

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