System and method for measuring coplanarity of integrated circuit (IC) pins through multistage reflection and raster imaging

Abstract

The invention discloses a system and a method for measuring the coplanarity of integrated circuit (IC) pins through multistage reflection and raster imaging. The system mainly comprises an IC chip dead load slant sliding feed mechanism, an external triggering synchronous control circuit, an IC chip pin imagingoptical path system, an image acquisition card and a personal computer (PC)-based intelligent visual inspection system. The IC chip pin imaging optical path system consists of two groups of mutually independent quasi-parallel blue-light light-emitting diode (LED) light sources, two rasters, and a plurality of reflectors and prisms which areorganically combined. A raster stripe images detected from the IC chip pins can be acquired throughthe imaging optical path system; and an image acquisition and analysis software system analyzes the images of the IC chip pins with raster stripes, evaluates the isometry of the pins in the images and the torsional characteristic of the raster stripes, and calculates a corresponding coplanarity error according to a corresponding f function mapping relation between a coplanarity error and the raster stripe curved degree. By the system and the method, two rows of pins of an IC chip are simultaneously imaged, the IC chip pins can be precisely detected through one-time imaging, the structure is compact, and the cost performance is high.

Description

Technical field: [0001] The patent of the invention belongs to the field of electronic integrated circuit packaging, and specifically relates to a new method and a new system for measuring the coplanarity of IC chip pins in electronic packaging. It is suitable for real-time monitoring of pin coplanarity of large-scale integrated circuits such as DIP (Dual In-line Package, dual in-line package), SOP (Small Out-Line Package, small outline package), and PFP (Plastic Flat Package, flat package). online measurement. Background technique: [0002] With the development of surface mount technology, SMD components have achieved rapid development. In the surface mount (SMT) production process of circuit boards, in order to ensure the quality of mounting, there are certain requirements for the size and shape accuracy of the IC chip pins, especially the vertical distance from the vertex of the IC chip pins to the pad. The distance (coplanarity) has certain accuracy requirements. If t...

AI Technical Summary

Problems solved by technology

[0011] The purpose of the present invention is to realize the online measurement of the coplanarity of IC chip pins, and overcome the shortcomings and shortcomings of the existing coplanarity measurement devices such as complex structure, bulky volume, high equipment manufacturing cost, slow detection speed and low detection accuracy.

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