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FPGA on-chip low power consumption system

A low-power, chip technology, applied in the field of microelectronics, can solve problems such as damage, no thermal analysis, and chip unrecoverable, to reduce power dissipation, improve safety and work stability, and reduce heat.

Active Publication Date: 2013-10-09
北京鸿智电通科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Without an accurate thermal analysis, the increase in heat can easily exceed the maximum allowable junction temperature, causing irreversible damage to the chip

Method used

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  • FPGA on-chip low power consumption system
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Embodiment Construction

[0021] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0022] Such as figure 1 As shown, the low power consumption system on the FPGA chip disclosed by the present invention includes a reference voltage circuit, a power-on reset module, a DLL power module, and an SRAM power module; the reference voltage circuit provides dual voltage references of 1.2V and 1.8V, and the reference voltage circuit uses The bandgap reference source is the core component, which generates a stable 1.2V reference voltage by using the 2.5V voltage input from the global power supply of the chip and the bandgap characteristics of the PNP transistor; the power-on reset module includes a The power-on reset circuit of the POR pulse signal of the electric reset also includes a reset signal detection circuit for ensuring the reset validity of the PO...

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Abstract

The invention discloses an FPGA on-chip low power consumption system which comprises a reference voltage circuit, a power on reset module, a DLL power supply module and an SRAM power supply module. The reference voltage circuit provides double voltage references of 1.2V and 1.8V. The power on reset module comprises a power on reset circuit which sends power on reset (POR) pulse signals when a chip power supply rises to 1.6V. The DLL power supply module comprises a voltage stabilizer which provides 2V voltages for a DLL relay chain. The SRAM power supply module obtains another voltage SRAMVDD from the chip power supply VDD through voltage conversion. The voltage SRAMVDD is higher than a voltage VDD. The voltage SRAMVDD and the voltage VDD are respectively added on different SRAM units. The voltage SRAMVDD is added on a source end and a substrate of a PMOS transistor of an SRAM unit at the same time. Dynamic switch power consumption and short circuit power of an FPGA chip are lowered, dynamic switch power consumption and static direct current power of an SRAM storage are lowered, and the safety and working stability of the FPGA chip are improved.

Description

technical field [0001] The invention relates to the field of microelectronics, in particular to an FPGA-on-chip low-power consumption system. Background technique [0002] The problem of power dissipation in integrated circuits is a thermal problem. So all problems related to heat may lead to changes in chip power consumption. But in the natural environment, heat problem is one of the most common phenomena. These problems also exist for semiconductor integrated circuits. Energy in nature is always being transformed. After the chip is powered on, a lot of electric energy has to be converted into heat energy. For relatively small chips, this converted energy will not cause fatal damage to the chip. But for large-scale chips, such as CPU, GPU, FPGA, the problem of excessive power consumption is inevitable, and the huge heat will cause serious and irreversible damage to the chip. Moreover, with the continuous advancement of semiconductor process technology and the continuou...

Claims

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Application Information

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IPC IPC(8): H03K19/177
Inventor 何弢
Owner 北京鸿智电通科技有限公司