Method and system for reducing soft error rate of processor

A soft error rate, processor technology, applied in the direction of electrical digital data processing, error detection/correction, instruments, etc., can solve problems such as incorrect instruction execution, achieve the effect of improving performance power consumption ratio and reducing soft error rate

Active Publication Date: 2013-10-23
INST OF COMPUTING TECH CHINESE ACAD OF SCI
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Problems solved by technology

Because an error in the program counter will almost c

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  • Method and system for reducing soft error rate of processor
  • Method and system for reducing soft error rate of processor
  • Method and system for reducing soft error rate of processor

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Embodiment Construction

[0035] The technical solutions of the present invention will be described in detail below in conjunction with the embodiments and the accompanying drawings.

[0036] figure 1 It is a flow chart of the method for reducing the soft error rate of the processor according to the present invention, including: the step of building a prediction model (S11), the step of identifying program fragments (S12), the step of obtaining statistical features (S13), and the step of predicting the best configuration (S14) and an adjustment step (S15).

[0037] The predictive model building step (S11), constructing a predictive model using machine learning methods to predict the optimal configuration of the processor that can reduce the soft error rate of the processor with low overhead.

[0038] Between the statistical feature space X and the processor optimal configuration space Y, a predictive model f:X→Y is constructed using machine learning methods. To build a predictive model, use x(x 1 ,x...

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Abstract

The invention discloses a method and system for reducing soft error rate of a processor. The method comprises the following steps: constructing a prediction model: adopting a machine learning method to construct the prediction model, so as to predict processor optimum configuration capable of reducing soft error rate of the processor with low cost; recognizing program segments: dividing a program into a plurality of continuous program segments during program running; obtaining statistical characteristics: obtaining the statistical characteristics of the program segments within a short period of time when the program segments are run initially; predicting optimum configuration: inputting the obtained statistical characteristics into the prediction model, so as to predict the processor optimum configuration corresponding to the program segments as predicting results; adjusting: according to the predicting results, adjusting processor components configuration, so as to reduce the soft error rate of the processor under the condition that performance power consumption ratio is maintained or improved. According to the method and the system for reducing soft error rate of the processor, the purpose that the reduction of soft error rate of the processor with low cost is achieved through dynamically adjusting the processor components configuration is achieved.

Description

technical field [0001] The invention relates to processor reliability technology, in particular to a method and system for reducing processor soft error rate with low overhead. Background technique [0002] As Moore's Law continues to be effective, the number of transistors integrated on a single chip still maintains an exponential growth trend. Semiconductor devices, especially processors, have been greatly improved in terms of functionality and performance. However, every technological innovation also introduces some new problems that hinder the development of technology. In recent years, soft errors caused by high-energy particles bombarding semiconductor devices causing logic bit flips have emerged. With the continuous development of chip technology, soft errors have become an important problem hindering the development of chips. [0003] Single logic bit flips can be caused when high-energy particles, such as neutrons from cosmic rays and alpha particles from packagi...

Claims

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Application Information

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IPC IPC(8): G06F11/00
Inventor 尹一笑陈云霁胡伟武
Owner INST OF COMPUTING TECH CHINESE ACAD OF SCI
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