Non-volatile memory device and method of operating the same

A non-volatile storage and device technology, applied in the field of semiconductor circuits, can solve the problems that PRAM does not support different storage units to set data and reset data, errors, read data damage, etc.

Inactive Publication Date: 2013-10-23
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Traditional PRAM does not support the operation of programming setting data and resetting data at the same time for different memory cells
Furthermore, when a conventional PRAM performs a read operation during a write operation, that is, when a read-while-write (RWW) operation is performed, if noise on the read path is generated by a signal on the write path, the read data may be corrupted by the noise, cause errors in RWW operation

Method used

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Embodiment Construction

[0039] figure 1 is a block diagram of the system 10 for explaining a method of programming a delay for a nonvolatile memory device 30 according to an exemplary embodiment. Throughout the specification, "exemplary" means an example or illustration. Also, in this specification, "programmed delay" refers to the amount of delay used in adjusting the generation timing of a set pulse and / or the generation timing of a reset pulse generated based on one of a plurality of pulses included in a set pulse. , delay duration, or delay information.

[0040] refer to figure 1 , the system 10 includes a tester 20 and a non-volatile storage device 30 . The tester 20 is configured to test the performance of the nonvolatile memory device 30 . From the perspective of the tester 20 , the nonvolatile memory device 30 may be, for example, a device under test (DUT), and the DUT may be a chip included in the wafer 15 indicated by a shaded area. The non-volatile memory device 30 may be, for example...

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Abstract

The invention provides a non-volatile memory device, including a set pulse generator configured to generate a set pulse, a reset pulse generator configured to generate a reset pulse based on the set pulse, and a write driver block configured to write second data to a second non-volatile memory cell using the reset pulse, while writing first data to a first non-volatile memory cell using the set pulse.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 10-2012-0037466 filed in the Korean Intellectual Property Office on Apr. 10, 2012, the entire contents of which are hereby incorporated by reference. technical field [0003] Exemplary embodiments relate to semiconductor circuits, and more particularly, to nonvolatile memory devices capable of generating a reset pulse based on a set pulse during a set (set) data / reset (reset) data simultaneous programming operation, operating nonvolatile A method for a volatile memory device, and an electronic device including a nonvolatile memory device. Background technique [0004] Chalcogenide alloys are used as phase change materials for phase change random access memory (PRAM). Due to Joule heating induced by the current or voltage supplied to the phase change material, the phase change material changes from a crystalline state (low resistance) to an amorphous s...

Claims

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Application Information

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IPC IPC(8): G11C13/00
CPCG11C7/22G11C13/0004G11C13/0061G11C29/021G11C13/0069G11C13/00G11C29/028G11C2013/0088G11C29/023G11C16/20G11C16/32
Inventor 权容震李光振金惠珍
Owner SAMSUNG ELECTRONICS CO LTD
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