Formation method of semiconductor structure

Abstract

A semiconductor structure forming method comprises the steps of providing a semiconductor substrate, wherein a semiconductor component is formed on the semiconductor substrate; forming a first medium layer on the semiconductor substrate, wherein the first medium layer covers the first semiconductor component, and a plug connected with the semiconductor component is formed in the first medium layer; forming second medium layers on the surface of the first medium layer and the surface of the plug; forming an opening exposing the surface of the plug in the second medium layer; after forming the opening, conducting first annealing on the semiconductor substrate; after conducting the first annealing, filling metal into the opening and forming a first metal mutual connecting layer. Before the first metal mutual connecting layer, the first annealing is conducted, so that inner stress between various materials on the semiconductor substrate is reduced, and the stacking effect of the inner stress is reduced after the first metal mutual connecting line is formed.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] With the advancement of semiconductor technology, the size of integrated circuits has become smaller and smaller. When the integration of integrated circuits increases, the surface of the chip cannot provide enough area to make the required interconnection lines. Therefore, most of the current VLSI structures use a multi-layer stacked metal interconnection structure. [0003] In the multi-layer stacked metal interconnection structure, each layer of metal interconnection layer includes several metal interconnection lines, and the metal interconnection lines in the same layer are separated by dielectric materials, and the metal interconnection lines in different layers The wires are also separated by dielectric materials, and the metal interconnection wires of different layers are connected by ...

AI Technical Summary

Problems solved by technology

Since the thermal expansion coefficients of the metal interconnection layer and the dielectric material are very different, when the ambient temperature of the multilayer stacked metal interconnection structure changes greatly, the thermal internal heat suffered by the metal interconnection line and the dielectric material The stress difference is also very large, causing the internal stress migration (Stress Migration, SM) of the multi-layer stacked metal interconnection structure, which will cause the wafer to deform, and in severe cases, the semiconductor device will fail.

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