A general bus conversion bridge ip core

Abstract

A novel general bus transforming bridge IP core comprises a plurality of bus modules of different protocols and a switching module, wherein the switching module comprises a plurality of memorizers, a data switching unit, a data analysis unit, a data package unit, a state register unit and an interruption control unit. Under the state that data switching is needed, the bus modules connected with a plurality of data sending parties respectively send first interruption requests to the interruption control unit, the interruption control unit modifies the value of the state register unit according to the first interruption requests, the data analysis unit reads data of the corresponding bus modules and then analyzes the data, the data switching unit transmits the analyzed data to the corresponding memorizers, the interruption control unit sends second interruption requests to corresponding data receiving parties, the data package unit reads data from the memorizers and packages the data into a needed data format, and the data receiving parties read the packaged data from the switching module.

Description

technical field [0001] The invention relates to the field of electrical communication, in particular to a universal bus conversion bridge IP core. Background technique [0002] In the field of electrical communication, especially in large-scale and complex communication systems, not only the amount of data is very large, but also the bus protocol used by each device is not completely the same. In order to meet the data exchange between these devices, it must be set in the system A bus protocol switching device. Taking the radar system as an example, each sub-module inevitably uses different bus protocols, so the resource management module must exchange bus protocols when controlling and exchanging data with each subsystem module. Generally, two methods are used to solve the bus conversion problem. The first method is that the resource management module integrates all bus protocols to be compatible with the bus protocols of other modules. The defect of this method is that it...

AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to: utilize the programmable characteristic of FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) and the advantage of parallel operation to design a kind of bus switching framework, in order to solve the reliable control of each submodule in the radar system and efficient data exchange

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