Partially-depleted silicon-on-insulator device structure

Abstract

The invention provides a partially-depleted silicon-on-insulator device structure. The partially-depleted silicon-on-insulator device structure comprises a semiconductor substrate, a device active area, a grid and a body contact active area. The semiconductor substrate comprises a bottom layer substrate, an insulation area buried layer and an upper layer substrate, wherein the bottom layer substrate, the insulation area buried layer and the upper layer substrate are sequentially stacked from bottom to top. The device active area is placed in the upper layer substrate and comprises a body region, a source region and a drain region. The grid stretches cross the device active area, the body region is placed below the grid, and the source region and the drain region are placed on the two sides of the grid respectively. The body contact active area is placed in the portion, on one side of the device active area in the width direction, of the upper layer substrate, the body contact active area is isolated from the drain region or the source region through a shallow insulation area, the shallow insulation area does not make contact with the insulation area buried layer, and the grid is electrically connected with the body contact active area. According to the partially-depleted silicon-on-insulator device structure, the evenness of starting of a partially-depleted silicon-on-insulator dynamic threshold transistor can be improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a partially depleted silicon-on-insulator device structure. Background technique [0002] In silicon on insulator (silicon on insulator, referred to as SOI) technology, the device is only manufactured in a thin silicon film on the surface, and the device is isolated from the underlying substrate by an oxide insulating region buried layer. The parasitic capacitance of this structure is small , so that the SOI device has the characteristics of high speed and low power consumption. Since the full dielectric isolation of SOI CMOS devices completely eliminates the parasitic latch-up effect of bulk silicon CMOS devices, SOI full dielectric isolation makes SOI technology have high integration density and good radiation resistance. Therefore, SOI technology is widely used in radio frequency, high voltage and anti-radiation. radiation etc. [0003] SOI MOS devices ar...

AI Technical Summary

Problems solved by technology

In the PDSOI MOSFET, due to the limited thickness of the gate 140, the parasitic resistance 190 of the body region 131 will make the dynamic threshold MOSFET turn on unevenly, thereby affecting the performance of the device

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