Low-power-consumption small-area capacitor array and reset method and logic control method thereof

Abstract

The invention discloses a low-power-consumption small-area capacitor array and a reset method and a logic control method of the low-power-consumption small-area capacitor array, and belongs to the technical field of low power consumption of successive approximation A / D converters. The low-power-consumption small-area capacitor array comprises a binary capacitor array, a switch array and four reference voltages and relates to a logic control mode combining capacitor upper plate sampling, switch initiation and capacitor all-in jump. The average consumed power of the capacitor array is 2.3% that of a traditional charge redistribution structure, and the area of the capacitor array is 12.5% that of the traditional charge redistribution structure, and the low-power-consumption small-area capacitor array has the advantages of being simple in structure, small in area, low in power consumption, flexible in match and the like. When the low-power-consumption small-area capacitor array is applied to the successive approximation ADCs, power consumption can be obviously reduced, area can be saved, matching performance and conversion precision can be improved, and moreover under the condition of the same accuracy, reduction of the scale of the capacitor array is favorable for improving A / D conversion efficiency.

Description

Technical field: [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a capacitor array with low power consumption and small area, a reset method and a logic control method thereof. Background technique: [0002] Successive approximation (SAR, SAR: Successive-Approximation-Register, successive approximation register) ADC is one of the commonly used ADC structure types. It has the advantages of simple structure and easy integration. The charge redistribution SAR ADC with capacitor array as the main structure relies on Its low power consumption advantage has been widely used. However, with the advancement of CMOS (CMOS: Complementary metal oxide semiconductor FET, Complementary Metal Oxide Semiconductor Field Effect Transistor) integrated circuit design technology and process feature size, the SoC scale is getting larger and larger, and the power consumption and The area has put forward stricter requirements. The scale of th...

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Problems solved by technology

On the one hand, due to the constraints of matching accuracy, not only the circuit area is large, the process cost is high, but also the dynamic power consumption of the capacitor array is large; on the other hand, the large-scale capacitor array leads to a large input capacitance of the SAR ADC, which affects the ADC Increased sampling rate

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