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A write-back method for error correction SRAM

A technology of writing address and writing signal, which is applied in the direction of response error generation and redundant code error detection, which can solve the problems of data error and low efficiency

Active Publication Date: 2016-06-22
北京中科微投资管理有限责任公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The SRAM using this scheme does not need to use an error correction circuit, and can also use an error correction circuit, but the efficiency of this scheme is relatively low
If the cycle is too short, most of the data stored in the SRAM during the cycle is still correct and does not need to be written back; if the cycle is too long, most of the data in the cycle has undergone multi-bit flips, and even writing back cannot avoid data errors

Method used

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  • A write-back method for error correction SRAM
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  • A write-back method for error correction SRAM

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Embodiment Construction

[0023] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, the specific implementation modes of the present invention will be described in detail below in conjunction with the accompanying drawings, so that the above-mentioned and other purposes, features and advantages of the present invention will be clearer. Like reference numerals designate like parts throughout the drawings. The drawings have not been drawn to scale, emphasis instead being placed upon illustrating the gist of the invention.

[0024] A write-back method of error correction SRAM, wherein, comprising the following steps:

[0025] Store the correct word code output into a redundant n-bit storage unit at the same time, and store its address signal in the latch;

[0026] The data stored in the n-bit storage unit is encoded according to the coding theory of the linear block code to generate redundant check bits;

[0027] XOR the redun...

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Abstract

The technical problem to be solved by the invention is to provide a write-back method of an error-correcting SRAM. By generating an error correction control signal through the redundant parity bit, and controlling the generation of a write-back write signal and a write-back address signal by the error correction control signal, the address signal is guaranteed to be unchanged, and stored in the n-bit storage unit in time The data is written into SRAM to complete the write-back function, ensuring that the data is not damaged and writing back according to the original address, ensuring that the original data is not damaged after being read, and avoiding cumulative errors.

Description

technical field [0001] The invention relates to a method for reliability of SRAM data, in particular to a method for preventing original data from being damaged when the SRAM data storage structure is read and written. Background technique [0002] Today's circuitry places stringent demands on the processing of large amounts of data, and as a result, demands on memory performance continue to increase. However, in the anti-radiation environment, the storage unit (bitcell) of the static random access memory (SRAM) will be upset (upset) to cause errors in stored data. Therefore, when designing the SRAM, an error detecting and correcting (EDAC) circuit should be introduced to write back data to meet the requirements of the circuit system. [0003] Usually the EDAC circuit can correct the error in one unit, and then output the correct codeword after correction, but how many errors it can correct depends on what error correction code is used. If the erroneous data stored in the ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/08
Inventor 刘鑫赵发展韩郑生
Owner 北京中科微投资管理有限责任公司