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Epitaxial wafer, its production method and super junction power device

A technology of power devices and production methods, which is applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as electrical failure, low collapse voltage of super-junction power devices, and failure to meet the use requirements, etc., to improve collapse The effect of uniform distribution of voltage and charge

Active Publication Date: 2017-05-24
SHANGHAI JINGMENG SILICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, if the first epitaxial layer whose resistivity is distributed radially from the edge of the epitaxial wafer is used, it will lead to electrical failure in the periphery, resulting in low breakdown voltage of super junction power devices, which cannot meet the requirements for use.

Method used

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  • Epitaxial wafer, its production method and super junction power device
  • Epitaxial wafer, its production method and super junction power device
  • Epitaxial wafer, its production method and super junction power device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0058] The epitaxial wafer is circular in shape. Cut along the thickness direction, the cross-sectional view is as follows Figure 4 As shown, an N-type substrate 1 and an N-type first epitaxial layer 2 are included. A single crystal silicon layer 5 is disposed between the N-type substrate 1 and the N-type first epitaxial layer 2 .

[0059] Its production steps include: Figure 4 As shown, an N-type substrate 1 is provided; the back of the N-type substrate 1 is oxidized to form an oxide layer 7; the edge of the oxide layer 7 is etched to a width L of 2 mm. A single crystal silicon layer 5 is deposited on the N-type substrate 1 ; the single crystal silicon layer 5 is arranged between the N-type substrate 1 and the N-type epitaxial layer 2 . The single crystal silicon layer 5 has a thickness of 4 μm. The single crystal silicon layer 5 is formed by the reaction of trichlorosilane and hydrogen at 1040° C. and deposited on the surface of the substrate 1 . A first epitaxial lay...

Embodiment 2

[0064] The production method is different from that of Example 1 in that the single crystal silicon layer 5 is formed by the reaction of trichlorosilane and hydrogen at 1045° C. and deposited on the surface of the substrate 1 . All the other structures and production methods are the same as in Example 1.

[0065] Such as Figure 9 Shown is the resistivity distribution diagram of the epitaxial layer of the epitaxial wafer produced in this embodiment. From Figure 9 It can be seen that the resistivity of the first epitaxial layer 2 is distributed concentrically. From the center of the circle, the resistivity non-uniformity of the first 30mm annular zone is 1.1%. The resistivity non-uniformity of the second 30mm annular zone is 1.2%. The resistivity non-uniformity of the third 30mm annular zone is 3.8%.

[0066] Figure 10 Shown is the electrical test diagram of the super-junction power device produced by using the epitaxial wafer in Example 2, and the black solid circle in...

Embodiment 3

[0068] The production method is different from that of Example 1 in that the single crystal silicon layer 5 is formed by the reaction of trichlorosilane and hydrogen at 1050° C. and deposited on the surface of the substrate 1 . All the other structures and production methods are the same as in Example 1.

[0069] Such as Figure 11 Shown is the resistivity distribution diagram of the epitaxial layer of the epitaxial wafer produced in this embodiment. From Figure 11 It can be seen that the resistivity of the first epitaxial layer 2 is distributed concentrically. From the center of the circle, the resistivity non-uniformity of the first 30mm annular zone is 1.0%. The resistivity non-uniformity of the second 30mm annular zone is 1.2%. The resistivity non-uniformity of the third 30mm annular zone is 3.7%.

[0070] Figure 12 Shown is the electrical test diagram of the super junction power device produced by using the epitaxial wafer in Example 3, and the black solid circle ...

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Abstract

The invention discloses an epitaxial wafer comprising a substrate and a first epitaxial layer; the epitaxial wafer is characterized in that the first epitaxial layer resistivity is distributed in a concentric circles shape. The resistivity of the epitaxial wafer is distributed in a concentric circles shape. A groove is etched and filled with epitaxial material, charge distribution is uniform, so electric property failure problem cannot happen. The epitaxial wafer can be used to improve collapse voltage of a super junction power device, and the collapse voltage can be improved by more than 50 volts. The collapse voltage of a super junction power device produced by an epitaxial wafer with non-concentric circles distribution is 580 volts; the collapse voltage of the super junction power device produced by the epitaxial wafer of the invention can increase to 630 volts.

Description

technical field [0001] The invention relates to an epitaxial wafer, its production method and a super junction power device. Background technique [0002] Compared with traditional power devices, super junction power devices have higher breakdown voltage and lower on-resistance. For super junction power devices, under the same on-resistance, the higher the breakdown voltage, the better. Such as figure 1 As shown, a schematic diagram of the structure of an epitaxial wafer used in one of the super junction power devices, which includes a substrate 1 with a first N-type epitaxial layer 2 on the substrate 1 . The N-type first epitaxial layer 2 has a groove (not shown in the figure), the second epitaxial layer 4 covers the surface of the first epitaxial layer 2 , and the second epitaxial layer 4 is embedded in the groove of the first epitaxial layer 2 . One of the main challenges of superjunction power devices is uniform charge distribution. In the process of super junction p...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/06H01L21/20
CPCH01L21/20H01L21/2053H01L29/0603H01L29/0634
Inventor 林志鑫钟旻远姚桢
Owner SHANGHAI JINGMENG SILICON CORP