A kind of i/o interface circuit of asynchronous sram

Abstract

The invention discloses an I / O interface circuit of an asynchronous SRAM, belonging to the technical field of SRAM data reading and writing. The interface circuit includes a read circuit and a write circuit; the output end of the read circuit is connected to the input end of the write circuit; the read circuit is connected to the enable signal, the data signal and the read signal; the write circuit is connected to the write signal . The I / O interface circuit of the asynchronous SRAM of the present invention controls the operation of the output data by using the enable signal and the read signal, and uses the write signal to control the write operation of the data, so that the read or write of the data is realized conveniently and quickly Operation; by introducing positive feedback in the read circuit, the accuracy of the level signal is enhanced; there is no path from the power supply VDD to the ground GND, which greatly reduces the power consumption of the read circuit; by using the read signal to control the transistor Turn on to speed up the response speed of the circuit.

Description

technical field [0001] The invention relates to the technical field of SRAM data reading and writing, in particular to an I / O interface circuit of an asynchronous SRAM. Background technique [0002] The I / O interface circuit of SRAM (Static Random Access Memory, SRAM) is bidirectional, and the data stored in SRAM can be used as input or output. In engineering applications, the driving problem of the signal should also be considered. figure 1 It is the I / O interface circuit diagram of the existing asynchronous SRAM, in the I / O interface circuit by designing the gate voltage V of the PMOS tube M1 b Make it work in a saturated state, which is equivalent to a constant current source, and M2~M5 constitute a differential signal amplifier; the differential amplified signal of In1 and In2 is output to the gate of M9, if it is high level, the drain terminal of M9 Pull down to the ground, and then output the correct signal to Out through the inverter INV; and the two groups of M6 an...

AI Technical Summary

Problems solved by technology

[0003] In order to solve the problems of large power consumption, poor reliability and unstable control of the existing I / O interface circuit of the asynchronous SRAM, the present invention provides an I / O interface circuit of the asynchronous SRAM, including a read circuit and a write circuit; The output end of the read circuit is connected to the input end of the write circuit; the read circuit is connected to the enable signal, the data signal and the read signal; the write circuit is connected to the write signal

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