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Methods of forming a metal silicide region in an integrated circuit

A technology of metal silicide and metal silicide layer, which is applied in the manufacture of circuits, electrical components, semiconductors/solid-state devices, etc., and can solve problems such as complicated and expensive steps

Inactive Publication Date: 2014-03-19
APPLIED MATERIALS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0002] Integrated circuit fabrication includes many steps that can be complex and expensive

Method used

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  • Methods of forming a metal silicide region in an integrated circuit
  • Methods of forming a metal silicide region in an integrated circuit
  • Methods of forming a metal silicide region in an integrated circuit

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Embodiment Construction

[0015] Methods for forming metal suicide regions in integrated circuits are disclosed herein. The method of the present invention advantageously reduces the number and / or complexity of process steps required to form metal suicide regions in an integrated circuit. For example, the use of silicide-resistive regions may eliminate the need for hard mask layers such as silicon nitride (SiN) or the like in the fabrication process. Furthermore, the method of the present invention can advantageously be used to control resistivity in resistive layers of integrated circuits. For example, doping with active dopants such as boron (B), phosphorus (P) or arsenic (As) can be used to control resistivity. For example, the resistivity can be controlled in the range from about 0.1 kohms per square to about 10 kohms per square without silicide formation, and when silicide is formed, the Resistivity is controlled down to about 20 ohms per square. Accordingly, embodiments of the present inventio...

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Abstract

Methods of forming a metal silicide region in an integrated circuit are provided herein. In some embodiments, a method of forming a metal silicide region in an integrated circuit includes forming a silicide-resistive region in a first region of a substrate, the substrate having the first region and a second region, wherein a mask layer is deposited atop the substrate and patterned to expose the first region; removing the mask layer after the silicide-resistive region is formed in the first region of the substrate; depositing a metal-containing layer on a first surface of the first region and a second surface of the second region; and annealing the deposited metal-containing layer to form a first metal silicide region in the second region.

Description

technical field [0001] Embodiments of the invention generally relate to methods of substrate processing for integrated circuits. Background technique [0002] Integrated circuit fabrication includes many steps that can be complex and expensive. For example, an exemplary process for forming a metal silicide in an integrated circuit includes the steps of: providing a substrate having a first region and a second region, and depositing a first patterned photoresist layer to expose the first region . The first region is doped with a dopant to control resistivity in the first region. Once doping of the first region is complete, the first patterned masking layer is removed and a second patterned masking layer is formed to expose the second region. The second patterned mask layer is a hard mask, such as silicon nitride (SiN). A metal layer, such as nickel (Ni), is deposited on top of the exposed second region, and the metal layer is annealed to form a metal suicide in the expose...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/24H01L21/324
CPCH01L21/28518
Inventor 迈克尔·G·沃德伊戈尔·V·佩德斯
Owner APPLIED MATERIALS INC