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Method for manufacturing semiconductor device

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc., can solve the problem of increasing the difficulty of the sidewall structure, and achieve the effect of reducing the difficulty of removal

Active Publication Date: 2014-03-26
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At the same time, since the silicon cap layer 106 has a considerable thickness, it increases the difficulty of removing the sidewall structure

Method used

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  • Method for manufacturing semiconductor device
  • Method for manufacturing semiconductor device
  • Method for manufacturing semiconductor device

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Embodiment Construction

[0024] In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

[0025] In order to fully understand the present invention, detailed steps will be presented in the following description to illustrate the method of forming embedded SiGe proposed by the present invention. Obviously, the practice of the invention is not limited to specific details familiar to those skilled in the semiconductor arts. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments besides these detailed descriptions.

[0026] It should be understood that when the terms "comp...

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Abstract

The invention provides a method for manufacturing a semiconductor device. The method comprises the following steps: providing a semiconductor substrate, wherein a grid structure is formed on the semiconductor substrate, and a side wall structure is formed on two sides of the grid structure; forming an embedded germanium-silicon layer of which the top part is not higher than the surface of the semiconductor substrate in the position of a source / drain region of the semiconductor substrate; removing the side wall structures; performing low-doped ion injection so as to form an inactivated low-doped source / drain area in the semiconductor substrate; forming another side wall structure on two sides of the grid structure; forming a silicon cap layer on the embedded germanium-silicon layer. Through the adoption of the method, damage to a grid hard shielding layer can be compensated in the process that the side wall structures on two sides of the grid structure are removed after the embedded germanium-silicon is formed, and the difficulty in eliminating the side walls is reduced.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a method for forming embedded silicon germanium. Background technique [0002] Embedded silicon germanium is a technology widely used in CMOS devices to apply compressive stress to the channel region of the PMOS part to improve its performance. There are many challenges in the process of forming the embedded silicon germanium, including the problems faced by the embedded silicon germanium itself, such as how to form embedded silicon germanium with a high content of germanium and how to control the embedded silicon germanium The occurrence of stacking fault defects, etc., and how to better integrate the process of forming the embedded silicon germanium with other processes used to form the CMOS device, for example, how to make the embedded silicon germanium closer to the trench area, forming embedded SiGe with a more ideal shape, controlling the thermal budget of the proce...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336
CPCH01L29/6653H01L29/66568H01L29/7848
Inventor 刘佳磊
Owner SEMICON MFG INT (SHANGHAI) CORP
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