Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which comprises a first region and a second region; forming a low-K dielectric layer on the surface of the substrate; carrying out the etching of the low-K dielectric layers in the first and second regions, forming a plurality of openings at the low-K dielectric layer in the first region, and forming a plurality of grooves at the low-K dielectric layer of the second region; placing metal in the first openings and the grooves, forming two opposite plate electrodes of a plurality of capacitors at the low-K dielectric layer in the first region, and forming a plurality of interconnection structures at the low-K dielectric layer of the second region; removing the low-K dielectric layer between the two opposite plate electrodes in the first region, and forming a second opening between the two opposite plate electrodes; placing a high-K dielectric layer in the second opening, wherein the high-K dielectric layer serves as the dielectric material layer of a capacitor. The method achieves the integrated manufacturing of capacitors and interconnection structures in the low-K dielectric layers, and reduces the area of the capacitors.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] With the continuous development of semiconductor integrated circuit technology, the size of semiconductor devices and the size of interconnection structures are continuously reduced, resulting in the gradual reduction of the spacing between metal wirings, and the dielectric layer used to isolate metal wirings is becoming more and more Thinner and thinner, this will cause crosstalk between metal connections. Reducing the dielectric constant K of the dielectric layer can solve the crosstalk problem, and can also effectively reduce the resistance-capacitance (RC) delay of the interconnection. Therefore, in deep submicron technology, low-K materials and ultra-low-K materials have been increasingly used in back-end interconnection processes. [0003] Capacitive components are often used a...

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Problems solved by technology

[0004] However, in the back-end process, although the capacitor (MIM capacitor) required by the integrated circuit can be fabricated in the low-K dielectric layer, the capacitance value per unit area is too small due to the influence of the low dielectric constant of the low-K material. As a result, the overall area of ​​the entire capacitor is larger, which reduces the integration of the circuit

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