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A Method for Restraining Threshold Voltage Drift of PMOS Devices

A threshold voltage drift and device technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as unfavorable device performance stability, metal ion contamination, and gate structure and morphology have a great influence, and reduce aggregation. risk, the effect of suppressing threshold voltage drift

Active Publication Date: 2016-04-13
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Although the above method can suppress the depletion of gate polysilicon, the newly introduced titanium is easily oxidized and expanded in the subsequent gate polysilicon re-oxidation (Re-oxidation) process, resulting in spherical protrusions (pilling), which It will greatly affect the morphology of the gate structure, which is not conducive to the stability of the device performance
At the same time, the introduction of titanium also poses a risk of metal ion contamination to products on the process line

Method used

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  • A Method for Restraining Threshold Voltage Drift of PMOS Devices

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Embodiment Construction

[0019] Such as image 3 Shown is the flow chart of the method of the embodiment of the present invention; the method for suppressing the threshold voltage drift of the PMOS device in the embodiment of the present invention includes the following steps:

[0020] Step 1, such as Figure 4A As shown, a gate oxide layer 2 and a gate polysilicon 3 are sequentially formed on a silicon substrate 1. After the gate polysilicon 3 is formed, boron ion implantation is performed for the first time, and the first boron ion implantation implants boron ions into the gate polysilicon and make the gate polysilicon a P-type doped structure. The implantation energy of the first boron ion implantation is 3KeV-8KeV, and the implantation dose is 1E14cm -2 ~1E16cm -2 .

[0021] Step two, such as Figure 4A As shown, metal tungsten silicide 4 is formed on the surface of the gate polysilicon 3 after the first boron ion implantation.

[0022] Step three, such as Figure 4B As shown, the second bo...

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Abstract

The invention discloses a method for inhibiting PMOS-device threshold-voltage drift. The method includes the following steps: performing boron ion injection in gate polysilicon; forming a metal tungsten silicide on the surface of the gate polysilicon; and performing boron ion injection on the metal tungsten silicide. In the method, boron doping is performed on the metal tungsten silicide through adoption of boron ion injection after growth of the metal tungsten silicide so that the boron doping concentration of the metal tungsten silicide approximates or reaches the solid solubility of boron atoms in the metal tungsten silicide. Because the boron doping concentration of the metal tungsten silicide already approximates or reaches the maximum, diffusion of boron in the gate polysilicon towards contact surfaces of the gate polysilicon and the metal tungsten silicide in a follow-up heating process is prevented so that a risk that boron atoms aggregate in the metal tungsten silicide is reduced and thus threshold-voltage drift of a PMOS device is effectively inhibited.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing process method, in particular to a method for suppressing the threshold voltage drift of a PMOS device. Background technique [0002] In the existing process, in order to facilitate the integration of NMOS devices, the gate polysilicon of PMOS devices adopts the same doping conditions as the gate polysilicon of NMOS devices, that is, both are N-type doped and require heavy doping, and the gate polysilicon of PMOS devices After N-type doping of extremely polysilicon, a P-type buried channel (buried channel) must be formed in the channel region to solve the problem of high threshold voltage (Vt) caused by N-type gate polysilicon, and the introduction of P-type buried channel will cause Large leakage current problem. In order to solve the problems of higher Vt and larger leakage current caused by the buried channel of the existing PMOS device, P-type boron impurities are used in th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/28
CPCH01L21/28044
Inventor 陈瑜马斌陈华伦罗啸
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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