A Method for Restraining Threshold Voltage Drift of PMOS Devices

A threshold voltage drift and device technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as unfavorable device performance stability, metal ion contamination, and gate structure and morphology have a great influence, and reduce aggregation. risk, the effect of suppressing threshold voltage drift
CN103681341BActive Publication Date: 2016-04-13SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Patent Information

Authority / Receiving Office
CN Β· China
Patent Type
Patents(China)
Current Assignee / Owner
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
Publication Date
2016-04-13

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Abstract

The invention discloses a method for inhibiting PMOS-device threshold-voltage drift. The method includes the following steps: performing boron ion injection in gate polysilicon; forming a metal tungsten silicide on the surface of the gate polysilicon; and performing boron ion injection on the metal tungsten silicide. In the method, boron doping is performed on the metal tungsten silicide through adoption of boron ion injection after growth of the metal tungsten silicide so that the boron doping concentration of the metal tungsten silicide approximates or reaches the solid solubility of boron atoms in the metal tungsten silicide. Because the boron doping concentration of the metal tungsten silicide already approximates or reaches the maximum, diffusion of boron in the gate polysilicon towards contact surfaces of the gate polysilicon and the metal tungsten silicide in a follow-up heating process is prevented so that a risk that boron atoms aggregate in the metal tungsten silicide is reduced and thus threshold-voltage drift of a PMOS device is effectively inhibited.
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Description

technical field

[0001] The invention relates to a semiconductor integrated circuit manufacturing process method, in particular to a method for suppressing the threshold voltage drift of a PMOS device. Background technique

[0002] In the existing process, in order to facilitate the integration of NMOS devices, the gate polysilicon of PMOS devices adopts the same doping conditions as the gate polysilicon of NMOS devices, that is, both are N-type doped and require heavy doping, and the gate polysilicon of PMOS devices After N-type doping of extremely polysilicon, a P-type buried channel (buried channel) must be formed in the channel region to solve the problem of high threshold voltage (Vt) caused by N-type gate polysilicon, and the introduction of P-type buried channel will cause Large leakage current problem. In order to solve the problems of higher Vt and larger leakage current caused by the buried channel of the existing PMOS device, P-type boron impurities are used in th...

Claims

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