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Serial communication protocols

A system clock and bit sequence technology, applied in the field of communication networks, can solve problems such as clock frequency mismatch, and achieve the effect of reducing the need for closely matching clocks

Active Publication Date: 2014-04-02
TEXAS INSTR INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Because each bit is synchronous, errors do not accumulate as each subsequent bit is received, and clock frequency mismatches greater than 20% can be tolerated when using 16x oversampling

Method used

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Embodiment Construction

[0035] The present invention proposes a novel technique for improving serial communication between devices. Multiple devices are connected in a ring. One device is defined as master and the rest are defined as slaves. The master device communicates with any slave device in the ring using a continuous dual frequency encoded bit stream. Serial data sent by the master device travels around the ring to each slave device, and then returns to the master device. The start of each bit is indicated by the master inverting the state of the line connected to the first slave in the ring. The master can signal a '1' bit by inverting the line a second time halfway through the pre-set bit time. Otherwise, the bit is interpreted as '0'. When data is being sent from a master to one or more slaves, each slave receives the data and sends that data unchanged to the next slave in the ring. When the master wishes to receive data returned by the slave, the master sends a placeholder bit with a ...

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Abstract

Systems and methods are disclosed which relate to improving synchronization of clocks between a sender and a receiver communicating via an asynchronous serial interface. In a ring topology (130), a master device (105) is connected to a plurality of slaves (S1-S3) communicating using a bi-frequency encoded bit stream. A host device communicates with the master device using a non-return-to-zero data encoding. Each slave (SI-S3) receives data from the master (105) and sends it to the next slave in the ring unaltered unless the master indicates a requirement for a particular data, and transmits placeholder bits with a value of 0 around the ring. A particular slave can 'fill-in' the placeholder bits with the information to be sent back to the master by inverting the placeholder bit. Clock synchronization between a receiving device and a transmitting device is improved using a fractional rate multiplier to generate a data sampling clock from a system clock. By adjusting the denominator, the sampling clock can be tuned to match the baud rate of the asynchronous serial data stream received from the transmitting device. Embodiments described include power management, data acquisition (DAQ), etc.

Description

technical field [0001] The present invention relates to communication networks and, in particular, to improving synchronization of elements in asynchronous serial data networks. Background technique [0002] In data communication there are two different formats used for data transfer: serial and parallel. In serial data transmission, data is transmitted one symbol at a time over a single communication channel or link such as a wire, fiber optic or wireless connection. In parallel data transmission, multiple symbols are transmitted simultaneously on corresponding multiple channels. Data is usually represented in binary format, and symbols can encode 1 or more bits of binary data, such as 1 or 0. [0003] One advantage of serial communication over parallel communication is that fewer physical resources are required to implement a serial interface, such as transmit and receive circuits, printed circuit board area, integrated circuit pins, connectors, and cables. In short, se...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L7/02H04L29/06H04L12/42
CPCH04N21/23602H03L7/00H04L12/42H04L12/403
Inventor J·M·罗斯
Owner TEXAS INSTR INC
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