Transistor and forming method thereof

Abstract

The invention relates to a transistor and a forming method thereof. The transistor comprises an epitaxial silicon layer having a first surface and a second surface opposite to the first surface; a gate structure located on the first surface of the epitaxial silicon layer, the gate structure including a gate medium layer located on the first surface of the epitaxial silicon layer and a gate electrode located on the surface of the gate medium layer; a fake gate located on the second surface of the epitaxial silicon layer, the position of the fake gate being corresponding to that of the gate structure; a first stress material layer located on a side wall and a top surface of the fake gate and the second surface of the epitaxial silicon layer; an oxide layer that cover the first stress material layer; and a second substrate bonded to the surface of the oxide layer. Through the fake gate located at the bottom of the gate structure and the first stress material layer located on the surface of the fake gate, stress is applied to a channel region of the transistor, and the magnitude of the stress of the channel region is increased.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a transistor and a forming method thereof. Background technique [0002] Metal-oxide-semiconductor (MOS) transistors are the most basic devices in semiconductor manufacturing. They are widely used in various integrated circuits. According to the main carrier and the type of doping during manufacturing, they are divided into NMOS and PMOS transistors. [0003] The prior art provides a method for manufacturing a MOS transistor. Please refer to Figure 1 to Figure 3 The schematic cross-sectional structure diagram of the manufacturing method of the MOS transistor in the prior art is shown. [0004] Please refer to figure 1 , providing a semiconductor substrate 100, forming isolation structures 101 in the semiconductor substrate 100, the semiconductor substrate 100 between the isolation structures 101 is an active region, and forming a doped well (not shown) in the active...

AI Technical Summary

Problems solved by technology

[0009] Currently, in order to improve the mobility of carriers in the channel region of the transistor, a tensile or compressive stress layer is formed on the sidewall and surface of the gate structure of the transistor, but the stress layer formed by this method is applied to the channel region. limited stress

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