Device isolation method in gate-last process

Abstract

The invention discloses a device isolation method in a gate-last process. The method includes: forming a gate stacking layer in a gate groove and on an inter-layer dielectric layer; forming a mask pattern on the gate stacking layer corresponding to the gate groove; using the mask pattern as a mask to etch the gate stacking layer until the upper surface of the inter-layer dielectric layer is exposed and forming a gate stacking structure; forming a second inter-layer dielectric layer on the inter-layer dielectric layer and the gate stacking structure; and etching the second inter-layer dielectric layer so as to form a plurality of contact holes and exposing the gate stacking structure. According to the device isolation method in the gate-last process, the mask is used to protect a metal gate and then redundant parts are etched so that isolation of devices is successfully performed and at the same time, a problem of peeling of the metal gate in a planarization process is prevented.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor device, in particular to a device isolation method in a gate-last process. Background technique [0002] With the successful application of high-K / metal gate engineering on the 45nm technology node, it has become an indispensable key modular project for the sub-30nm technology node. At present, only Intel, which adheres to the high-K / last metal gate (HK / MG gate last) route, has achieved success in mass production of 45nm and 32nm. In recent years, industry giants such as Samsung, TSMC, and Infineon, which have followed the IBM industry alliance, have also shifted the focus of previous development from high-K / gate first to gate last engineering. [0003] Usually, in the HK / MG Gate Last process, the electrode of the gate stack (Gate Stack) is made of Al material. But recently, W, as another Gate Stack electrode material, has become a research hotspot in the international semiconductor ...

AI Technical Summary

Problems solved by technology

[0008] From the above, the purpose of the present invention is to overcome the above-mentioned technical difficulties and propose a new device isolation method in the gate-last process, which not only successfully isolates devices, but also avoids the metal gate during the planarization process. stripping problem

Images