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Delay time adjusting circuit, delay time adjusting method and integrated circuit

A technology for delay time and circuit adjustment, applied in electrical components, electronic switches, pulse processing, etc., can solve problems such as increased circuit loss and cost overhead, interference of capacitor charging current, unfavorable circuit design, etc.

Active Publication Date: 2014-06-18
FAIRCHILD SEMICON SUZHOU
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since the charging time of the capacitor depends on the capacity of the capacitor and the magnitude of the charging current, when the charging current is small, a capacitor with a larger capacity is required, which will increase circuit loss and cost overhead, which is not conducive to circuit design
[0003] In addition, because the capacity of the capacitor and the magnitude of the charging current are easily interfered by the external circuit, there will be a large error, which will lead to a low delay time accuracy of the delay circuit

Method used

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  • Delay time adjusting circuit, delay time adjusting method and integrated circuit
  • Delay time adjusting circuit, delay time adjusting method and integrated circuit
  • Delay time adjusting circuit, delay time adjusting method and integrated circuit

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Embodiment Construction

[0024] Today's delay circuits, such as figure 1 As shown, it includes: a current source Q1, a capacitor C1, a first resistor R1, a second resistor R2, and a comparator P1; the current source Q1 charges the capacitor C1, and the first resistor R1 and the second resistor R2 divide the battery voltage. And the voltage on the second resistor R2 is input to the negative pole of the comparator P1; when the voltage on the capacitor C1 is greater than the voltage on the second resistor R2, the comparator P1 changes from outputting a negative signal to an outputting positive signal, wherein the capacitor C1 The time from 0 to greater than the voltage on the second resistor R2 is the delay time of the delay circuit;

[0025] Here, when the charging current provided by the current source Q1 is less than or equal to 100nA, in the case of the same delay time, a large-capacity capacitor C1 is required, which will increase circuit loss and cost overhead, which is not conducive to circuit des...

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Abstract

The invention discloses a delay time adjusting circuit. A reference signal circuit in the delay time adjusting circuit generates more than one reference signal to a digital to analog conversion circuit; an input signal circuit generates an input signal to the digital to analog conversion circuit; the voltage of input signal is determined by the required delay time; the digital to analog conversion circuit compares the voltage of the input signal and the voltage of more than one reference signal, and outputs a digital signal to a digital logic chip; the digital logic chip determines the delay time according to the digital signal, and then the delay is started. The invention also discloses a delay time adjusting method and an integrated circuit. By adopting the scheme, the delay time can be digitally determined, the adjusting accuracy of the delay time is improved, and the circuit loss and cost are reduced by changing the voltage to adjust the delay time of the input signal.

Description

technical field [0001] The invention relates to delay technology, in particular to a delay time adjustment circuit, method and integrated circuit. Background technique [0002] At present, the delay time of the delay circuit is usually based on the charging time of the capacitor. For the adjustment of the delay time of the delay circuit, it is necessary to adjust the parameters of the resistance-capacitance (RC) element of the delay circuit, and then adjust the charging time of the capacitor. . Since the charging time of the capacitor depends on the capacity of the capacitor and the magnitude of the charging current, when the charging current is small, a capacitor with a larger capacity is required, which will increase circuit loss and cost overhead, which is not conducive to circuit design. [0003] In addition, because the capacity of the capacitor and the magnitude of the charging current are easily interfered by the external circuit, there will be a large error, which w...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K17/28
CPCH03K5/131
Inventor 孙伟明林明泉黄雷王一祝鹏
Owner FAIRCHILD SEMICON SUZHOU