A Resynthesis Method for Heterogeneous Logic Units in Integrated Circuits
A logic unit and integrated circuit technology, applied in the field of microelectronics, can solve the problem that the process mapping algorithm cannot effectively use the logic resources of the CLB structure, achieve broad market prospects and application value, reduce the circuit area, and reduce the number of LUTs.
Active Publication Date: 2017-03-29
INST OF MICROELECTRONICS CHINESE ACAD OF SCI +1
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[0011] In view of this, the main purpose of the present invention is to provide a re-synthesis method for heterogeneous logic units of integrated circuits, to solve the problem that the process mapping algorithm cannot effectively utilize all logic resources in the CLB structure
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[0049] In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings, so that those skilled in the art can better understand the present invention and implement it , but the examples cited are not intended to limit the present invention. While illustrations of parameters including particular values may be provided herein, it should be understood that parameters need not be exactly equal to the corresponding values, but rather may approximate the values within acceptable error margins or design constraints.
[0050] The present invention provides a resynthesis method for heterogeneous logic units of integrated circuits, comprising the following steps:
[0051] Step A, arranging all nodes in the netlist after process mapping in reverse topological order;
[0052] The netlist after proces...
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The invention discloses a method for re-integrating heterogenous logic units of integrated circuits. The method includes arraying all nodes in technologically mapped net lists in inverse topological orders; computing cut of each node; computing a function f(X) of each cut; decomposing the functions f(X); carrying out Boolean machining on the functions f(X) by the aid of LUTs (lookup tables) structures with equivalent functionality. The method has the advantages that all logic resources in the heterogenous logic units can be sufficiently utilized by the aid of the method, so that the service LUT quantity can be reduced; the method can be widely applied to re-integrating the heterogenous logic units after technological mapping is carried out, the areas of the circuits can be reduced under the condition that circuit delay is undamaged, the design cost can be lowered, and the method has a broad market prospect and high application value.
Description
technical field [0001] The invention relates to the technical field of integrated circuit design and electronic design automation in the field of microelectronics, in particular to a resynthesis method for heterogeneous logic units of integrated circuits. Background technique [0002] In recent years, field programmable gate array (Field Programmable Gate Array, FPGA) has significantly improved in terms of speed, capacity and functionality, so it gradually replaces application specific integrated circuit (ASIC) in many application fields. The application of FPGA and Widespread ubiquity has brought great flexibility to the design of digital systems. The logic block structure (configurable logic block, CLB) of most current FPGAs is based on a lookup table (lookup table, LUT). A k-input LUT (k-LUT) contains 2k static random access memory (SRAM) units, which can be Realize the logic that any number of inputs is not greater than k. In order to further improve the configuration ...
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IPC IPC(8): G06F17/50
Inventor 张峰王作建吴洋于芳刘忠立
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI