Controller and controlling method for intensive data frame queues

A queue controller and control method technology, applied in data conversion, electrical digital data processing, instruments, etc., to achieve the effect of reducing storage resource requirements, strong scalability, and good scalability

Active Publication Date: 2014-07-02
AVIC NO 631 RES INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] In order to solve the above-mentioned technical problems existing in the background technology, the present invention provides a kind of close memory arrangement that can realize data frame, can improve the limited storage resource utilization rate, solve the bottleneck problem of storage resource effectively, be beneficial to in the existing FPGA chip Based on the realization of high-performance switches and communication interfaces, as well as an intensive data frame queue controller and control method that can reduce the difficulty and cost of hardware design

Method used

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  • Controller and controlling method for intensive data frame queues
  • Controller and controlling method for intensive data frame queues

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Embodiment Construction

[0041] see figure 1, the intensive data queue controller is based on dual-port memory and FIFO, adopts a chain management structure to arrange data frames tightly, and implements a data frame queue management control circuit based on FPGA design. The circuit consists of five parts: input control unit, output control unit, dual-port memory, FIFO, and control register group.

[0042] in:

[0043] Dual-port memory: A shared memory resource used to store the length and content of data frames.

[0044] FIFO: used to store the first address of the data frame, and the data frame address indicates the offset address of the data in the dual-port memory. FIFO adopts a first-in-first-out policy to realize sequential storage of multiple data frame addresses.

[0045] Control register group: used to store the ring queue, including queue head address QueueHeadPtr, queue tail address QueueTailPtr, queue length QueueLength, and maximum data frame length Frame_MAXLen. Controlling the acces...

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Abstract

The invention relates to a controller and a controlling method for intensive data frame queues. The controller for the intensive data frame queues comprises an FIFO used for storing initial addresses of all data orderly, a sharing storage source double-port storer used by a storer to store the length and the content of data frames and dedicated control logic used for realizing data frame queue control management, wherein the FIFO and the double-port storer are connected with the dedicated control logic respectively. The controller and the controlling method for the intensive data frame queues can realize tight storage and array of data frames, can improve the utilization rate of limited storage resources, effectively solve the bottleneck problems of resource storage, are favorable to realizing a high-performance interchanger and communication ports on the basis of an existing FPGA chip and can reduce hardware designing difficulty and cost.

Description

technical field [0001] The invention belongs to the technical field of computer control, and relates to an intensive data frame queue controller and a control method, in particular to an intensive data frame queue controller and a control method for data frame queue management in switches and communication nodes. Background technique [0002] In the design of high-speed communication systems, in order to ensure the transmission efficiency and communication service quality of the system, it is necessary to use a large number of storage resources to store data frames in switches and communication nodes to alleviate the mismatch between communication interfaces and upper-layer processing access rates. [0003] The hardware design of the communication system is often implemented by FPGA programmable devices, but due to the limitation of the chip process, the internal storage resources of the FPGA are limited, so the FPGA storage resources become the bottleneck restricting the des...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F5/01
Inventor 王红春牛文生黄韬邱征
Owner AVIC NO 631 RES INST
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