A network physical isolation device
A physical isolation and network technology, applied in the protection of internal/peripheral computer components, etc., can solve problems such as difficulty in closing or opening, computer intrusion risk, etc., and achieve the effect of reducing risks
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Embodiment 1
[0012] Embodiment 1: The south bridge chip of the computer motherboard has multiple GPIO ports, which can be used as input or output high and low levels. The onboard network card controller on the motherboard can receive external signals to close or start the Bluetooth connection, and the 51st pin of the MINI-PCIE slot on the motherboard also has the ability to receive external signals to close the wireless WIFI network card in the slot and the function of the bluetooth network card. The source of the NMOS transistor Q4 is grounded, its gate is connected to the second GPIO port 2 of the south bridge chip PCH, and its drain is connected to the 51st pin of the MINI-PCIE slot and the 20th pin of the onboard network card controller. The six pins and the cathode of LED D5 are connected together. The first GPIO port 1 of the south bridge chip is connected to one end of the switch SW. The other end of the switch SW is connected to the anode of the light emitting diode D5 and one en...
Embodiment 2
[0015] Example 2: The emitter of the NPN transistor T4 is grounded, its collector is connected to the second GPIO port 2 of the south bridge chip PCH, and its base is connected to the 51st pin of the MINI-PCIE slot, the on-board network card The twenty-sixth pin of the controller and the negative electrode of the light-emitting diode D5 are connected together. The first GPIO port 1 of the south bridge chip is connected to one end of the switch SW. The other end of the switch SW is connected to the anode of the light emitting diode D5 and one end of the bias resistor. The other end of the bias resistor R is connected to the power supply VCC.
[0016] The switch SW is in a normally open state. When the user presses the switch SW to close it, the first GPIO port 1 is pulled up to a high level through the bias resistor R, and the south bridge chip simultaneously changes the voltage of the second GPIO port 2 to a high level. Therefore, the transistor T4 is turned on, and the fif...
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