Field-programmable gate array (FPGA) layout method based on simulated annealing/tempering

Abstract

The invention discloses a field-programmable gate array (FPGA) layout method based on simulated annealing / tempering. A method of mixing simulated annealing and simulated tempering is used. Firstly, a traditional simulated annealing method is utilized to obtain a best solution current_best which can be found by simulated annealing, the temperature 44 DEG C (temp44) is recorded when the receiving rate of the solution is 44%, proper temperature gradient (t1, t2,```, tm) from temp44 to a freezing point temperature is established, then a tempering method is started to be simulated according to the temperature gradient, if a solution which is better than the current_best is found in the process, the solution better than the current_best replaces the current_best, and a finally obtained current_best is a required optimal solution. The FPGA layout method based on simulated annealing / tempering is applied to a layout tool of electronic design automation (EDA) software which supports FPGA development, a finally layout result is good in stability, meanwhile, the qualities of circuits can be improved, time delay of key routes is reduced, and a final distributed wire length is improved.

Description

technical field [0001] The invention belongs to the technical field of computers, and in particular relates to a field programmable gate array layout method based on simulated annealing / tempering. Background technique [0002] In recent years, with the rapid development of integrated circuit technology, FPGA (Field Programmable Gate Array) field programmable gate array, because of its high integration, rich logic resources, flexible design and reconfigurability, is widely used in the aerospace field and The field of national defense is widely used. Every year, my country needs to import a large number of FPGA (Field Programmable Gate Array) field programmable gate array chips and supporting software from abroad. However, the domestic FPGA (Field Programmable Gate Array) field programmable gate array industry needs to be developed. The main reason for the development of the domestic FPGA (Field Programmable Gate Array) field programmable gate array industry is the lack of self-...

AI Technical Summary

Problems solved by technology

It aims to solve the problem that the traditional simulated annealing method is very sensitive to parameters in the application of FPGA (Field Programmable Gate Array) field programmable gate array layout, and the problem that it cannot cross the energy barrier in the low temperature stage and wanders in the local optimal solution

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