Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

AES algorithm-oriented anti-power attack method and circuit implementation

An anti-power consumption and algorithm technology, applied in the direction of encryption devices with shift registers/memory, etc., can solve the problem of high attack efficiency, achieve the effect of small area cost, strong scalability, and improve the ability to resist power consumption attacks

Active Publication Date: 2017-02-15
SOUTHEAST UNIV
View PDF2 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At the same time, the implementation of power consumption analysis attack is relatively simple, and the attack efficiency is very high, which is an important threat to the security of cryptographic algorithm circuits.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • AES algorithm-oriented anti-power attack method and circuit implementation
  • AES algorithm-oriented anti-power attack method and circuit implementation
  • AES algorithm-oriented anti-power attack method and circuit implementation

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0045] Below in conjunction with accompanying drawing and specific embodiment, further illustrate the present invention, should be understood that these embodiments are only for illustrating the present invention and are not intended to limit the scope of the present invention, after having read the present invention, those skilled in the art will understand various aspects of the present invention Modifications in equivalent forms all fall within the scope defined by the appended claims of this application.

[0046] Such as figure 1 As shown, the original AES block encryption algorithm consists of 3 parts, including the initial XOR with the key, 9 cycles of round operations in the middle, and transformation at the end of the 10th round. The initial key of AES is 128 bits, and each round requires a 128-bit subkey k i (i=0,...,10), a total of eleven subkeys, the subkeys are obtained by expanding the initial key.

[0047] The 9 rounds of round operations in the middle of the A...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a power attack prevention method oriented at an AES algorithm and a circuit achieving method of the power attack prevention method oriented at the AES algorithm. According to the basic principle, a control module and redundancy registers are added to an AES algorithm circuit. The AES algorithm selects the position of a register storing middle calculation data in each turn according to a zone bit generated by the control module, so that the middle data of each turn of encryption operation are alternatively stored in the different registers, the Hamming distance of the middle data of the AES algorithm is effectively hidden, and the AES algorithm can resist power analysis attacks based on a Hamming distance model. The power attack prevention method oriented at the AES algorithm and the circuit achieving method of the power attack prevention method oriented at the AES algorithm have the advantages of being high in flexibility, small in area cost, high in power attack resistance and the like, and provide a good resolution scheme for designing safe chips.

Description

technical field [0001] The invention relates to the technical fields of integrated circuit hardware implementation and information security, in particular to an anti-power consumption attack method for advanced encryption algorithm (Advanced Encryption Standard, AES) hardware circuits. Background technique [0002] With the rapid development of Internet technology and information technology, information encryption technology has very important applications in many fields. Information security products represented by cryptographic devices have penetrated into all aspects of national security and people's lives. Various cryptographic chips based on algorithms such as AES and RSA have been extensively researched and developed. [0003] With the development of information technology, cryptographic chips are also facing more and more security risks. In recent years, side-channel attack (Side-Channel Attack, SCA, also known as "side-channel attack") has become a new cryptographic...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H04L9/06
Inventor 单伟伟孙华芳伏星源
Owner SOUTHEAST UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products