A circuit for a memory write operation

A technology for writing data and storing devices, which is applied in static memory, digital memory information, information storage, etc., and can solve problems such as DRAM limitations

Active Publication Date: 2017-03-01
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] A typical DRAM memory cell has only one transistor and one capacitor, so it offers a high level of integration for large amounts of information storage; however, DRAM needs to be constantly refreshed, and its slow speed tends to limit DRAM to computer main memory

Method used

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  • A circuit for a memory write operation
  • A circuit for a memory write operation
  • A circuit for a memory write operation

Examples

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Embodiment Construction

[0040] The following disclosure provides a number of different embodiments, or examples, for implementing various elements of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are examples and not intended to be limiting.

[0041] For some memory devices such as SRAM, the reduced supply voltage (i.e., lower CVDD voltage "LCV") generated by the supply voltage circuit compared to the nominal supply voltage reduces the write data operation cycle time, resulting in faster write speed. As long as the reduced supply voltage is not reduced enough to affect signal integrity, noise margin, etc., thereby interfering with the integrity of write data operations, the transition between logic low and logic high voltage values ​​associated with the reduced supply voltage is less , correspondingly takes less time.

[0042] One approach to achieving a reduced supply voltage for SRAM write operations has significant ...

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Abstract

A pulsed dynamic LCV circuit for improving write operations for SRAM. The pulsed dynamic LCV circuit includes voltage adjustment circuitry having a plurality of selectable reduced supply voltages and timing adjustment circuitry having a plurality of selectable logical state transition timings for adjustably controlling the voltage and timing of a transition from a selected reduced supply voltage back to a nominal supply voltage. The voltage adjustment circuitry has a plurality of selectable transistors that when individually selected have a cumulative effect to pull the reduced supply voltage down further. The timing adjustment circuitry has a plurality of selectable multiplexers that when individually selected for a delayed voltage transition have a cumulative effect to delay return of voltage supplied to SRAM from a reduced supply voltage to a nominal supply voltage.

Description

technical field [0001] The present invention relates generally to the field of semiconductor technology, and more particularly, to semiconductor circuits and methods of operating the same. Background technique [0002] Many electronic devices, such as desktop computers, laptop computers, tablet computers, and smartphones, employ integrated and / or discrete semiconductor memory devices to store information. These semiconductor memory devices are classified into volatile or nonvolatile types. Volatile memories lose their stored information when power is removed, while non-volatile memories retain their stored information even after power is removed. Volatile memory includes random access memory (RAM), which is further divided into subcategories including static random access memory (SRAM) and dynamic random access memory (DRAM). [0003] A typical DRAM memory cell has only one transistor and one capacitor, so it offers a high level of integration for large amounts of informat...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/419
CPCG11C7/22G11C11/419G11C2207/2227
Inventor 杨荣平李政宏黄家恩吴福安邱志杰
Owner TAIWAN SEMICON MFG CO LTD
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