Device for scheduling and buffering data packets and method thereof

Abstract

The invention discloses a device for scheduling and buffering data packets, which comprises the components of: a packet data first input first output (FIFO) module, a packet header data FIFO module and a business processing module; wherein the packet data FIFO module is used for extracting packet header information of a data packet and transmitting the packet header information to the packet header data FIFO module for storage when the data packet data are scheduled and read out; and is furthermore used for acquiring packet length information and cyclic redundancy check code (CRC) verification result when a packet tail mark is scheduled and read out. The packet header data FIFO module is used for storing the packet header information. When the packet data FIFO module reads out the packet tail mark which corresponds with the packet header information, the packet header information is read out. The business processing module is used for generating descriptor information according to the packet header information, the packet length information and the CRC verification result. The invention simultaneously discloses a method for scheduling and buffering data packets. The device and the method according to the invention have functions of: saving a large mount of resources stored in a chip, reducing time delay of the data packet in the chip, reducing chip cost, and improving area and power consumption of the chip.

Description

technical field [0001] The invention relates to the field of data communication, in particular to a device and method for scheduling and buffering data packets. Background technique [0002] At present, in the traditional traffic management chip, for the business processing of data packets, it is necessary to determine the data packet needs according to the packet header information, packet length information and cyclic redundancy check code (CRC, Cyclic Redundancy Check) check result of the data packet. No cache is required. Both the packet length information and the CRC check result can only be calculated after receiving the complete data packet, that is to say, they can only be obtained at the end of the packet. [0003] In practical applications, it is usually necessary to open up a port data first-in-first-out (FIFO, First In First Out) memory for each input port to store at least one complete data packet, extract packet header information and obtain packet length info...

AI Technical Summary

Problems solved by technology

With the rapid growth of network services, the number of input ports of traffic management chips is increasing, and the length of data packets is getting larger and larger, and the requirements for chip storage capabilities are also getting higher and higher, which in turn increases the cost of chips

[0004] In addition, after the data packets are processed by predetermined rules in the business processing module, tens or even hundreds of bytes of descriptor information will be generated. The descriptor information is usually stored inside the traffic management chip, which invisibly increases the storage capacity of the chip. burden

Images