A Network-on-Chip Mapping Method Based on Discrete Firefly Algorithm

A technology of firefly algorithm and network-on-chip, which is applied in the field of network-on-chip mapping based on discrete firefly algorithm, which can solve the problems of not being able to obtain the global optimal solution, restricting the exploration space of the algorithm, and local optimum of the optimization result, etc.

Active Publication Date: 2017-02-22
黄山市开发投资集团有限公司
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  • Abstract
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Problems solved by technology

The disadvantage of this method is that, for particle swarm optimization (PSO), random factors are not added to the position update formula of the PSO algorithm, so it is easy to make the optimization result fall into the local optimum, and it is impossible to obtain the global optimal solution; In the process of generating initial samples, the exploration space of the algorithm is limited, which may result in the inability to obtain the global optimal solution

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  • A Network-on-Chip Mapping Method Based on Discrete Firefly Algorithm
  • A Network-on-Chip Mapping Method Based on Discrete Firefly Algorithm
  • A Network-on-Chip Mapping Method Based on Discrete Firefly Algorithm

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example 1

[0213] To verify the invention, the invention will be used to solve the mapping problem of a typical multimedia benchmark VOPD application. The VOPD application can be divided into 16 tasks and assigned to 16 cores for execution (assuming that the tasks are assigned to the IP cores with the same serial number for execution), such as figure 1 As shown, the mapping problem at this time is how to allocate these 16 IP cores to a NoC with a scale of 4×4×1.

[0214] Before applying the present invention, the objective function is defined as the fluorescence brightness I of the kth firefly k (t k ):

[0215]

[0216] In formula (6), v i,j is the i-th communication node r mapped with an IP core i and the jth communication node r mapped with an IP core j The amount of communication between, h i,j is the i-th communication node r mapped with an IP core i (coordinates (i x ,i y ,i z )) and the jth communication node r mapped with IP core j (coordinates (j x ,j y ,j z )) ...

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Abstract

The invention discloses a NoC (network-on-chip) mapping method based on a discrete firefly algorithm. The NoC mapping method is characterized by comprising the following steps: step 1, performing parameter definition; step 2, initializing a firefly individual set and parameters; step 3, detecting iteration end conditions, carrying out step 9 if the iteration end conditions are met, otherwise, carrying out step 4; step 4, acquiring the optimal firefly of the Gth iteration and the globally optimal firefly; step 5, judging the movement condition of one firefly individual; step 6, traversing the firefly individual set and judging the movement conditions of all the firefly individuals according to the step 5, and carrying out step 8 after the traversing is finished; step 7, updating the firefly individuals; step 8, updating the optimal firefly of the Gth iteration; and step 9, acquiring the optimal mapping scheme. The NoC mapping method based on the discrete firefly algorithm can shorten the optimizing time, improve the solving precision and acquire the better mapping result.

Description

technical field [0001] The invention belongs to the technical field of network communication, in particular to an on-chip network mapping method based on a discrete firefly algorithm. Background technique [0002] With the continuous development of the semiconductor chip manufacturing process level, the area of ​​the semiconductor wafer is increasing, the feature size of the integrated circuit is getting smaller and smaller, and the transistor resources on the integrated circuit are increasing. The increase in the number of integrated transistors on a single chip makes the system composed of multiple chips develop towards a single-chip System-on-Chip (System-on-Chip). At present, the interconnection between various functional components and processor cores on most SoCs is based on the bus structure. However, with the improvement of people's demand for chip functions, there are more and more SoC integrated components. The traditional bus structure is Disadvantages in scalabi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/24G06F17/50G06F15/173
Inventor 杜高明刘鑫张多利宋宇鲲欧阳昊尹勇生
Owner 黄山市开发投资集团有限公司
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