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Delay phase-locked loop and method for improving accuracy of delay phase-locked loop

A phase-locked loop, precision technology, applied in the direction of automatic power control, electrical components, etc., can solve problems such as large power consumption and layout area, and achieve the effect of improving accuracy and precision

Active Publication Date: 2014-10-29
XI AN UNIIC SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In the existing DLL structure, in order to obtain a higher-precision clock, it is often necessary to increase the number of bits in the DLL fine-tuning chain to achieve it, which requires large power consumption and layout area

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  • Delay phase-locked loop and method for improving accuracy of delay phase-locked loop

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Embodiment Construction

[0027] The core of the present invention lies in the newly-added intermediate phase generating circuit. The function of the intermediate phase generating circuit is to generate a clock of an intermediate phase according to the input odd clock and even clock, and change the original input phase difference of t into an output clock. A clock with a phase difference of t / 2. In this way, the precision of the original delayed clock can be changed from t / n to t / 2n accordingly, and the precision is doubled.

[0028] The even clock of the input signal is input to inverter 0, and the odd clock of the input signal is input to inverter 20 at the same time; the even clock is output to inverters 1, 2, 3 and inverters 11, 12, 13; The odd clock is output to the inverters 21, 22, 23 and inverters 14, 15, 13 after passing through the inverter 20; the inverters 12, 15 are output to the inverter 13 at the same time, generating a simultaneous even The clock signal controlled by clock and odd cloc...

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Abstract

The invention provides a delay phase-locked loop and a method for improving the accuracy of the delay phase-locked loop, wherein the accuracy of the delay phase-locked loop is at least doubled on the premise of increasing a domain area and power consumption as little as possible. The delay phase-locked loop comprises a DLL delay chain, wherein the DLL delay chain comprises a DLL coarse tuning chain and a DLL fine tuning chain. The delay phase-locked loop is characterized in that a middle phase generator used for generating the middle phase of the odd clock and the even clock of an input clock signal is arranged between the DLL coarse tuning chain and the DLL fine tuning chain. The method for improving the accuracy of the delay phase-locked loop comprises is generating two clock signals which are an odd-even clock and a middle clock, through the even clocks and the odd clocks of two input clock signals, wherein the phase difference of the odd-even clock and the middle clock is one half of the phase difference of the even clock and the odd clock.

Description

technical field [0001] The invention provides a delay phase-locked loop and a method for improving the precision of the delay phase-locked loop. Background technique [0002] Delay-locked loop (DLL) is widely used in microprocessors, memory interfaces, interfaces between chips, and clock distribution networks of large-scale integrated circuits. It is mostly used for clock synchronization to solve the problem of clock skew, making There is enough margin in the clock delay between them, so as to improve the timing function of the system. [0003] With the increase of the clock frequency of the application system, the requirement for the DLL adjustment accuracy is getting higher and higher, because it directly determines the maximum phase detection error of the DLL. A traditional DLL consists of a DLL delay chain (including a coarse-tuning chain and a fine-tuning chain), a feedback delay, a phase detector, a DLL controller, and an output driver. It works as follows: [0004]...

Claims

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Application Information

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IPC IPC(8): H03L7/085
Inventor 郭晓锋刘成
Owner XI AN UNIIC SEMICON CO LTD