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Array substrate, preparation method of array substrate and display device

An array substrate and substrate technology, which is applied in semiconductor/solid-state device manufacturing, optics, instruments, etc., can solve the problems of affecting voltage uniformity, high resistance, and affecting the uniformity of alignment film, so as to improve aperture ratio, ensure uniformity, The effect of reducing the total resistance

Active Publication Date: 2014-12-10
BOE TECH GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Connecting the common electrodes 11 in the same column through via holes will inevitably affect the aperture ratio of the entire array substrate due to the existence of the via holes, and will also affect the uniformity of the alignment film formed above the via holes; and each common electrode 11 uses a bridge Therefore, the resistance is large, which affects the uniformity of the applied voltage of each common electrode 11, resulting in poor display

Method used

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  • Array substrate, preparation method of array substrate and display device
  • Array substrate, preparation method of array substrate and display device
  • Array substrate, preparation method of array substrate and display device

Examples

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Embodiment 1

[0035] to combine Figures 3 to 5 As shown, this embodiment provides an array substrate, which includes a substrate, a common electrode layer 10, a first insulating layer 50, and a gate layer sequentially arranged on the substrate; wherein, the common electrode layer 10 includes a The plurality of corresponding common electrodes 11 and the common electrode connecting portion 13, each of the common electrodes 11 is connected through the common electrode connecting portion 13; the gate line layer is electrically insulated from the common electrode layer 10 through the first insulating layer 50 open.

[0036] It should be noted that the common electrode 11 and the common electrode connecting portion 13 can be connected as a complete surface structure, that is to say, the common electrode 11 and the common electrode connecting portion 13 are only different in area distribution and function, and the materials of the two The same, of course, the common electrode connecting portion ...

Embodiment 2

[0039] to combine Figures 3 to 5 As shown, this embodiment provides an array substrate, which is based on the array substrate in Embodiment 1, and the array substrate in this embodiment further includes elements such as thin film transistors and data line layers. In order to describe the structure of the array substrate in this embodiment more clearly, the following describes an array substrate including bottom-gate TFTs as an example, but the types of TFTs are not limited to bottom-gate TFTs, and top-gate TFTs are also feasible. , will not be described in detail here.

[0040] The array substrate in this embodiment includes: a base;

[0041] A common electrode layer 10 disposed on the substrate, wherein a plurality of L-shaped openings 14 for defining each of the common electrodes are disposed in the common electrode connection portion of the common electrode layer; the first insulating layer disposed on the common electrode layer 50, wherein a common electrode contact reg...

Embodiment 3

[0049] This embodiment provides a method for preparing an array substrate. The array substrate may be the array substrate described in Embodiment 1 or 2, and the steps specifically include:

[0050] Step 1. Form a pattern including a common electrode layer on the substrate through a patterning process. The common electrode layer includes a plurality of common electrodes corresponding to each pixel area and a common electrode connecting portion, and each of the common electrodes is connected through the common electrode. department connection.

[0051] It should be noted that the common electrode and the common electrode connection part can be connected as a complete surface structure, that is to say, the common electrode and the common electrode connection part are only different in area distribution and function, and the materials of the two are the same. Of course, the common electrode connection part may also have a structure with openings, but it only needs to ensure the e...

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Abstract

The invention provides an array substrate, a preparation method of the array substrate and a display device and belongs to the technical field of display. The problem that an existing array substrate is low in aperture opening ratio can be solved. The array substrate comprises a substrate, a common electrode layer, a first insulation layer and a grid line layer, wherein the common electrode layer, the first insulation layer and the grid line layer are sequentially arranged on the substrate. The common electrode layer comprises multiple common electrodes corresponding to pixel areas and common electrode connecting portions, wherein the common electrodes are connected through the common electrode connecting portions. The grid line layer is electrically insulated and separated from the common electrode layer through the first insulation layer. The array substrate has high aperture opening ratio.

Description

technical field [0001] The invention belongs to the field of display technology, and in particular relates to an array substrate, a preparation method thereof, and a display device. Background technique [0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD for short) is an important flat panel display device. According to the direction of the electric field driving the liquid crystal, it can be divided into a vertical electric field type and a horizontal electric field type. The vertical electric field type requires the formation of pixel electrodes on the array substrate and the common electrode on the color filter substrate, such as the commonly used TN mode; while the horizontal electric field type requires the formation of pixel electrodes and common electrodes on the array substrate at the same time, such as the ADS mode (advanced hyperdimensional field transformation mode). ADS refers to the core technology of planar electric field wide viewing angle-Advanced...

Claims

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Application Information

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IPC IPC(8): H01L27/12H01L21/77G02F1/1362G02F1/1368
Inventor 陈华斌
Owner BOE TECH GRP CO LTD
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