Delay method and delay circuit for input under-voltage protection circuit

Abstract

The invention aims to provide a delay circuit for an input under-voltage protection circuit. The delay circuit comprises a sampling voltage setup module and a pulse output control module. The sampling voltage setup module sets up a sampling voltage Vp by enabling a voltage VFB of an output voltage feedback end to follow up a voltage Vss of a soft starting end; the pulse output control module receives the sampling voltage Vp and compares the sampling voltage Vp with a set value prior to outputting signals to control on/off of a GATE end. The delay circuit for the input under-voltage protection circuit has the advantages that before finishing of soft starting and after arrival of under-voltage protection signals, the GATE end is free of output, and accordingly an output voltage of a power source cannot rise instantly, and influences on post-stage circuits due to false triggering can be avoided.

Description

technical field [0001] The invention relates to an integrated circuit, in particular to a control chip with an input undervoltage protection circuit. Background technique [0002] The Chinese invention patent application published on August 13, 2014 with the publication number CN103986320 discloses a switching power supply remote control circuit, which has an undervoltage protection function, such as figure 1 As shown, it includes switching power supply control circuit 1, voltage sampling circuit 2 and remote control port circuit 3. Among them, the switching power supply control circuit 1 includes a control IC, which is an existing switching power supply control chip, which can output driving pulses with a certain frequency and a certain duty ratio according to the state of the circuit. The chip has an undervoltage protection function and is The undervoltage protection function is realized by detecting the input current of the undervoltage protection terminal UVP. [0003]...

AI Technical Summary

Problems solved by technology

[0005] But to do a delay circuit, when the chip is started or the module is reset, the capacitor, D flip-flop, counter, etc. must be initialized inside the chip, and because when the chip is started or the module is reset, it is necessary to ensure that the chip works normally and does not enter any protection state, so it must be initialized to the non-input undervoltage state, but initialized to the non-input undervoltage state, there will be a problem: if image 3 In the timing diagram shown, ENP_lv represents the low-voltage module initialization signal, which is high after initialization; VIN_fault_L represents the input undervoltage detection signal, which is active at low level; UVIN_L represents the undervoltage protection control signal, which is active at low level; GATE is the output pulse Signal

But during this period, once the input voltage is lower than the set undervoltage point, the input voltage Vin

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