Split type data flow controllable observable high-speed serial receiving device

Abstract

The invention relates to a split type data flow controllable observable high-speed serial receiving device. The split type data flow controllable observable high-speed serial receiving device comprises a device body, wherein a differential signal input port is arranged on the device body. The split type data flow controllable observable high-speed serial receiving device is characterized in that an ASIC receiving assembly is arranged on the differential signal input port; a communication port of the ASIC receiving device is connected with an off-chip buffering assembly; accordingly an integral SerDes receiving circuit can be achieved by adopting ASCI and an on-chip structure does not comprise an on-chip buffering module, clock driving mainly depends on data recovery, and the clock domain is simplified and a sequential logic design is simplified due to the fact that the number of clocks is reduced by one. Additionally, the off-chip elastic buffering module is achieved through FPGA and accordingly the configurability and the observability of the off-chip elastic buffering module are greatly improved.

Description

technical field [0001] The invention relates to a serial receiving device, in particular to a split-type data stream controllable and observable high-speed serial receiving device. Background technique [0002] High-speed (data rate above GHz) serial communication, such as backplane-to-backplane and chip-to-chip communication, requires the support of SerDes transceiver modules. Under the existing technical conditions, the transceiver modules above GHz can only be realized with ASIC chips. Existing commercial SerDes chips and reusable IP are similar to a black box, and it is difficult to control and observe the data flow inside it. When designing the high-speed IO protocol stack, the effective transmission rate of the channel can be improved by optimizing the TLP (Transaction Layer Packet) packet length and the clock compensation sequence transmission frequency. This requires a device to control and observe the internal data flow of the SerDes receiving module in real time....

AI Technical Summary

Problems solved by technology

Such a design has the following limitations: Since the elastic buffer module is on-chip of the high-speed serial receiving module, its configurability and observability are poor; and the bit width and depth of the on-chip elastic buffer module are limited, This limits the size of the largest TLP packet that the receiving module can receive (TLP packets cannot be truncated by other information); in this structure, there are three clock domains on the chip: data recovery clock, local crystal oscillator clock, and system clock PCLK

This patent does not solve the limitations of the existing high-speed serial receiver modules pointed out above

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