CRC (Cyclic Redundancy Check) method for SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) configuration refreshment

Abstract

The invention relates to a CRC (Cyclic Redundancy Check) method for SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) configuration refreshment. By studying the format, storage format and failure modes of an SRAM type FPGA configuration file and adopting a method which calculates and compares SRAM type FPGA read-back configuration frames with CRC codes prestored in a PROM in real time, the invention puts forward and implements the CRC method for SRAM type FPGA configuration refreshment. The method adopts the form of CRC check codes to realize the device independence of FPGA configuration information check, meanwhile, an enable flag and an obtainment flag are set, so that the application requirement of different-rate, large-data volume check is met, the CRC check of read-back data is implemented in real time in the read-back process, and thereby the object of saving memory resources and processing time is achieved. In addition, because a table lookup-based byte type CRC algorithm is used by the method, the independent division and management of resources is fast and efficient, and the operation speed and the operating frequency are increased.

Description

technical field [0001] The invention relates to a CRC verification method for SRAM FPGA configuration refresh, in particular to a method for quickly reading back an SRAM FPGA configuration file and verifying a calculated and generated CRC code in real time under the condition of limited logic resources. Background technique [0002] The SOC in the SoC central control unit of the subsystem of the aerospace flight tester is the first domestic attempt to use the SRAM FPGA in the spacecraft control computer. Since the SRAM FPGA is susceptible to errors caused by single event effects, the aerospace industry with high requirements for reliability The application needs to dynamically refresh the configuration file and read back the error detection, making the SRAM FPGA read-back verification technology one of the key and new technologies. The full-text read-back comparison needs to consume a lot of storage space, which is not suitable for limited software and hardware resources. sp...

AI Technical Summary

Problems solved by technology

[0002] The SOC in the SoC central control unit of the subsystem of the aerospace flight tester is the first domestic attempt to use SRAM-type FPGA in the space vehicle control computer. Because the SRAM-type FPGA is susceptible to errors caused by single event effects, the aerospace industry with high requirements for reliability The application needs to dynamically refresh the configuration file and read back the error detection, making the SRAM type FPGA read-back verification technology one of the key and new technologies. The full-text read-back comparison needs to consume a lot of storage space, which is not suitable for limited software and hardware resources. space mission applications

At the same time, since the implementation of inherent error detection resources in FPGA is not disclosed, it is difficult to verify the reliability and security of using inherent error detection resources

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