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flash memory controller

A flash memory and controller technology, applied in static memory, memory system, read-only memory, etc., can solve the problem of limited number of pins

Active Publication Date: 2018-04-10
SK 海尼克斯存储技术公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the number of pins on a device of a given size is limited, and therefore some of the functions of the chip in the package may need to be controlled by multiplexed devices

Method used

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Embodiment Construction

[0037] The exemplary embodiments may be better understood with reference to the drawings, but these embodiments are not intended to be limiting in nature. The same numbered elements in the same or different drawings perform equivalent functions. Elements can be numbered or designated by acronyms or both, and the choice between representations is made for clarity only, so that elements designated by numbers and designated by acronyms or alphanumeric indicators The same element of the should not be distinguished on that basis.

[0038] It will be appreciated that the method and the devices shown in the figures may be configured or embodied in machine-executable instructions (eg software) or in hardware or in a combination of both. Machine-executable instructions can be used to make general-purpose computers, special-purpose processors (such as DSPs), or array processors acting on instructions perform the functions described herein. Alternatively, operations may be performed by sp...

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PUM

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Abstract

Apparatus and methods for managing operation of a plurality of flash memory (FLASH) chips provide a physical layer (PHY) interface to a flash memory circuit having a plurality of flash memory chips having a common interface bus. The device has a PHY for controlling the voltage on the interface pins according to a microprogrammed state machine. An ongoing data transfer on the bus may be interrupted to execute another command to another chip on the shared bus, and the data transfer may resume after completion of the other command.

Description

[0001] This application claims the benefits of US 61 / 650,604 filed on May 23, 2012 and US 13 / 833,643 filed on March 15, 2013, both of which are incorporated herein by reference. Technical field [0002] This application may involve the storage of data in a computer memory system. Background technique [0003] NAND flash memory (FLASH) memory is electrically organized into multiple blocks on a die (chip), and multiple dies can be combined into a package, which can be called a flash memory circuit. The chip can have more than one plane so that erase, write and read operations can be handled separately. The block is composed of multiple pages, and the page is composed of multiple sectors. Some of the terms in this term set are legacy from hard disk drive (HDD) technology; however, as used in flash memory devices, some adaptations have been made. NAND flash memory is characterized in that data can be written to sectors of the memory, or a set of consecutive sectors including pages. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/06G06F13/14
CPCG06F12/0246
Inventor D.G.皮纳特利
Owner SK 海尼克斯存储技术公司