Manufacturing method of printed circuit board with low warpage and high flatness
A technology of printed circuit board and manufacturing method, which is applied in the directions of printed circuit manufacturing, printed circuit, multilayer circuit manufacturing, etc. The effect of sharing stress residuals, improving warpage, and improving flatness
Active Publication Date: 2018-01-30
GUANGZHOU FASTPRINT CIRCUIT TECH +2
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Problems solved by technology
Such requirements, for conventional symmetrical structures (see attached figure 1 ) is no problem, but when the Probe Card structure is more complex and the asymmetry is more obvious, it is easy to cause warpage and flatness control to exceed the standard
The traditional method is to stack directly, and the circuit layer and the prepreg are laminated at intervals. Due to the difference in the residual copper rate on each layer of the circuit layer, the board thickness after stacking is different, and the flatness is reduced.
Method used
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Embodiment Construction
[0020] Embodiments of the present invention are described in detail below:
[0021] refer to figure 2 and image 3 , the manufacturing method of the printed circuit board with low warpage and high flatness of the present invention, it comprises the following steps:
[0022] Step S1, the step of optimizing the inner layer graphics, laying copper as much as possible in the non-functional area, so that the entire inner layer structure presents a symmetrical structure as much as possible, and the copper surface is evenly distributed;
[0023] Step S2, the plate stacking step, adopts spaced plate stacking to effectively buffer uneven pressure and uneven temperature caused by asymmetry;
[0024] Step S3, optimizing the lamination step, this step S3 is carried out after the S2 lamination step, through optimizing the lamination program to form a plurality of multi-layer boards, namely the first multi-layer board, the second multi-layer board, and the third multi-layer board board ...
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The invention discloses a method for manufacturing a printed circuit board low in warping degree and high in flatness. The method is characterized in that the working procedure that copper is evenly and symmetrically laid on an inner-layer board is implemented, and inner-layer patterns are optimized; an interval type stacking working procedure is adopted, circuit layers and semi-curing glue can be slowly bonded, even if the residual copper rates of parts on the circuit layers are different, the difference in the thickness of a stacked board can be avoided, and the flatness is guaranteed; slow cooling is adopted for the multi-layer board whole pressing working procedure, and the pressing working procedure is optimized. In general, the method has the advantages that the design of interval type board stacking and inner-layer pattern file optimizing and the pressing process mode are adopted, residual stress caused by an asynchronous structure of the whole board is effectively shared, the warping degree is improved, and the flatness condition is improved.
Description
technical field [0001] The invention relates to a process method of a printed circuit board, in particular to a method for manufacturing a printed circuit board requiring low warpage and high flatness. Background technique [0002] With the development of smart mobile terminals such as smartphones and tablet computers in terms of miniaturization, intelligence, and energy saving, the requirements for high performance and integration of chips have shown a clear trend, and the technical requirements for chip manufacturers are also increasing. The more stringent, therefore, the chip also presents the characteristics of diversification and fast replacement, and the manufacturing technology requirements for the wafer board used for bare chip testing, also known as the probe card test board (Probe Card) are also increasing. higher. At this time, it is an inevitable trend to have more and more strict requirements on the warpage and flatness of the Probe Card, which can improve the ...
Claims
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IPC IPC(8): H05K3/00H05K3/46
CPCH05K3/4611H05K2203/06
Inventor 袁凯华李艳国刘昭亮
Owner GUANGZHOU FASTPRINT CIRCUIT TECH